From 0b7b17502300f7e7788fa5f1eab1147a960ede3c Mon Sep 17 00:00:00 2001 From: Shay Drory Date: Mon, 13 Jul 2026 11:43:19 +0300 Subject: [PATCH 1/2] net/mlx5: Drop redundant esw_cap, reuse e_switch_cap esw_manager_vport_number{,_valid} and merged_eswitch were read through a separate mlx5_ifc_esw_cap_bits struct, but these bits live in the e-switch capability that mlx5_ifc_e_switch_cap_bits already describes (both overlay the same QUERY_HCA_CAP op_mod 0x9 output). Add esw_manager_vport_number{,_valid} to mlx5_ifc_e_switch_cap_bits at the same offsets, drop the redundant mlx5_ifc_esw_cap_bits and its hca_cap_union member, and switch the only user (hws/cmd.c) to capability.e_switch_cap. Signed-off-by: Shay Drory Reviewed-by: Yevgeny Kliteynik Signed-off-by: Tariq Toukan Link: https://patch.msgid.link/20260713084320.1015240-2-tariqt@nvidia.com Reviewed-by: Jacob Keller Signed-off-by: Leon Romanovsky --- .../mellanox/mlx5/core/steering/hws/cmd.c | 6 +++--- include/linux/mlx5/mlx5_ifc.h | 21 +++++-------------- 2 files changed, 8 insertions(+), 19 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c index e624f5da96c8..8fae90101653 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c @@ -1172,13 +1172,13 @@ int mlx5hws_cmd_query_caps(struct mlx5_core_dev *mdev, } if (MLX5_GET(query_hca_cap_out, out, - capability.esw_cap.esw_manager_vport_number_valid)) + capability.e_switch_cap.esw_manager_vport_number_valid)) caps->eswitch_manager_vport_number = MLX5_GET(query_hca_cap_out, out, - capability.esw_cap.esw_manager_vport_number); + capability.e_switch_cap.esw_manager_vport_number); caps->merged_eswitch = MLX5_GET(query_hca_cap_out, out, - capability.esw_cap.merged_eswitch); + capability.e_switch_cap.merged_eswitch); } ret = mlx5_cmd_exec(mdev, in, sizeof(in), out, out_size); diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 695c86ee6d7a..9c8dbf29f1ef 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1042,20 +1042,6 @@ struct mlx5_ifc_wqe_based_flow_table_cap_bits { u8 reserved_at_1c1[0x1f]; }; -struct mlx5_ifc_esw_cap_bits { - u8 reserved_at_0[0x1d]; - u8 merged_eswitch[0x1]; - u8 reserved_at_1e[0x2]; - - u8 reserved_at_20[0x40]; - - u8 esw_manager_vport_number_valid[0x1]; - u8 reserved_at_61[0xf]; - u8 esw_manager_vport_number[0x10]; - - u8 reserved_at_80[0x780]; -}; - enum { MLX5_COUNTER_SOURCE_ESWITCH = 0x0, MLX5_COUNTER_FLOW_ESWITCH = 0x1, @@ -1096,7 +1082,11 @@ struct mlx5_ifc_e_switch_cap_bits { u8 log_max_esw_sf[0x5]; u8 esw_sf_base_id[0x10]; - u8 reserved_at_60[0x7a0]; + u8 esw_manager_vport_number_valid[0x1]; + u8 reserved_at_61[0xf]; + u8 esw_manager_vport_number[0x10]; + + u8 reserved_at_80[0x780]; }; @@ -3859,7 +3849,6 @@ union mlx5_ifc_hca_cap_union_bits { struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; - struct mlx5_ifc_esw_cap_bits esw_cap; struct mlx5_ifc_e_switch_cap_bits e_switch_cap; struct mlx5_ifc_port_selection_cap_bits port_selection_cap; struct mlx5_ifc_qos_cap_bits qos_cap; From bee40a7d0bd1263934f99054db037cdd4a33fd86 Mon Sep 17 00:00:00 2001 From: Cosmin Ratiu Date: Mon, 13 Jul 2026 11:43:20 +0300 Subject: [PATCH 2/2] net/mlx5: Add PSP related fields to the mlx5_ifc This adds: - misc_parameters_6, containing a few fields for matching PSP headers. As this is the last misc_parameters field defined, retire the old optimization added in commit [1] to not touch the reserved part. - PSP decap action. - PSP SPI header field pointer. [1] commit 667cb65ae5ad ("net/mlx5: Don't store reserved part in FTEs and FGs") Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Link: https://patch.msgid.link/20260713084320.1015240-3-tariqt@nvidia.com Reviewed-by: Jacob Keller Signed-off-by: Leon Romanovsky --- .../net/ethernet/mellanox/mlx5/core/fs_core.h | 12 +----------- include/linux/mlx5/device.h | 1 + include/linux/mlx5/mlx5_ifc.h | 17 +++++++++++++++-- 3 files changed, 17 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h index dbaf33b537f7..906584345a02 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h @@ -214,17 +214,7 @@ struct mlx5_ft_underlay_qp { u32 qpn; }; -#define MLX5_FTE_MATCH_PARAM_RESERVED reserved_at_e00 -/* Calculate the fte_match_param length and without the reserved length. - * Make sure the reserved field is the last. - */ -#define MLX5_ST_SZ_DW_MATCH_PARAM \ - ((MLX5_BYTE_OFF(fte_match_param, MLX5_FTE_MATCH_PARAM_RESERVED) / sizeof(u32)) + \ - BUILD_BUG_ON_ZERO(MLX5_ST_SZ_BYTES(fte_match_param) != \ - MLX5_FLD_SZ_BYTES(fte_match_param, \ - MLX5_FTE_MATCH_PARAM_RESERVED) +\ - MLX5_BYTE_OFF(fte_match_param, \ - MLX5_FTE_MATCH_PARAM_RESERVED))) +#define MLX5_ST_SZ_DW_MATCH_PARAM MLX5_ST_SZ_DW(fte_match_param) struct fs_fte_action { int modify_mask; diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index 07a25f264292..8cb321a9fb3d 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1171,6 +1171,7 @@ enum { MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4, MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5, MLX5_MATCH_MISC_PARAMETERS_5 = 1 << 6, + MLX5_MATCH_MISC_PARAMETERS_6 = 1 << 7, }; enum { diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 9c8dbf29f1ef..c7206a9d6731 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -508,7 +508,8 @@ struct mlx5_ifc_flow_table_prop_layout_bits { u8 reformat_l2_to_l3_audp_tunnel[0x1]; u8 reformat_l3_audp_tunnel_to_l2[0x1]; u8 ignore_flow_level_rtc_valid[0x1]; - u8 reserved_at_70[0x8]; + u8 reserved_at_70[0x7]; + u8 reformat_del_psp_transport[0x1]; u8 log_max_ft_num[0x8]; u8 reserved_at_80[0x10]; @@ -798,6 +799,15 @@ struct mlx5_ifc_fte_match_set_misc5_bits { u8 reserved_at_100[0x100]; }; +struct mlx5_ifc_fte_match_set_misc6_bits { + u8 reserved_at_0[0x1a]; + u8 psp_version[0x4]; + u8 reserved_at_1e[0x2]; + + u8 reserved_at_20[0x1e0]; +}; + + struct mlx5_ifc_cmd_pas_bits { u8 pa_h[0x20]; @@ -2342,7 +2352,7 @@ struct mlx5_ifc_fte_match_param_bits { struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; - u8 reserved_at_e00[0x200]; + struct mlx5_ifc_fte_match_set_misc6_bits misc_parameters_6; }; enum { @@ -6988,6 +6998,7 @@ enum { MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, + MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_6 = 0x7, }; struct mlx5_ifc_query_flow_group_out_bits { @@ -7249,6 +7260,7 @@ enum mlx5_reformat_ctx_type { MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, + MLX5_REFORMAT_TYPE_REMOVE_PSP_TRANSPORT = 0x16, }; struct mlx5_ifc_alloc_packet_reformat_context_in_bits { @@ -7372,6 +7384,7 @@ enum { MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, MLX5_ACTION_IN_FIELD_PSP_SYNDROME = 0x71, + MLX5_ACTION_IN_FIELD_PSP_HEADER_1 = 0x78, }; struct mlx5_ifc_alloc_modify_header_context_out_bits {