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ice: redesign dpll sma/u.fl pins control

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DPLL-enabled E810 NIC driver provides user with list of input and output
pins. Hardware internal design impacts user control over SMA and U.FL
pins. Currently end-user view on those dpll pins doesn't provide any layer
of abstraction. On the hardware level SMA and U.FL pins are tied together
due to existence of direction control logic for each pair:
- SMA1 (bi-directional) and U.FL1 (only output)
- SMA2 (bi-directional) and U.FL2 (only input)
The user activity on each pin of the pair may impact the state of the
other.

Previously all the pins were provided to the user as is, without the
control over SMA pins direction.

Introduce a software controlled layer of abstraction over external board
pins, instead of providing the user with access to raw pins connected to
the dpll:
- new software controlled SMA and U.FL pins,
- callback operations directing user requests to corresponding hardware
  pins according to the runtime configuration,
- ability to control SMA pins direction.

Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
This commit is contained in:
Arkadiusz Kubalewski
2025-04-22 18:01:47 +02:00
committed by Tony Nguyen
parent 9acae9e2e2
commit 2dd5d03c77
3 changed files with 936 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/net/ethernet/intel/ice/ice_dpll.c
+913 -14
View File
File diff suppressed because it is too large Load Diff
drivers/net/ethernet/intel/ice/ice_dpll.h
+22 -1
View File
@@ -8,6 +8,18 @@
#define ICE_DPLL_RCLK_NUM_MAX 4
/**
* enum ice_dpll_pin_sw - enumerate ice software pin indices:
* @ICE_DPLL_PIN_SW_1_IDX: index of first SW pin
* @ICE_DPLL_PIN_SW_2_IDX: index of second SW pin
* @ICE_DPLL_PIN_SW_NUM: number of SW pins in pair
*/
enum ice_dpll_pin_sw {
ICE_DPLL_PIN_SW_1_IDX,
ICE_DPLL_PIN_SW_2_IDX,
ICE_DPLL_PIN_SW_NUM
};
/** ice_dpll_pin - store info about pins
* @pin: dpll pin structure
* @pf: pointer to pf, which has registered the dpll_pin
@@ -31,7 +43,12 @@ struct ice_dpll_pin {
struct dpll_pin_properties prop;
u32 freq;
s32 phase_adjust;
struct ice_dpll_pin *input;
struct ice_dpll_pin *output;
enum dpll_pin_direction direction;
u8 status;
bool active;
bool hidden;
};
/** ice_dpll - store info required for DPLL control
@@ -93,14 +110,18 @@ struct ice_dplls {
struct ice_dpll pps;
struct ice_dpll_pin *inputs;
struct ice_dpll_pin *outputs;
struct ice_dpll_pin sma[ICE_DPLL_PIN_SW_NUM];
struct ice_dpll_pin ufl[ICE_DPLL_PIN_SW_NUM];
struct ice_dpll_pin rclk;
u8 num_inputs;
u8 num_outputs;
int cgu_state_acq_err_num;
u8 sma_data;
u8 base_rclk_idx;
int cgu_state_acq_err_num;
u64 clock_id;
s32 input_phase_adj_max;
s32 output_phase_adj_max;
bool generic;
};
#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
drivers/net/ethernet/intel/ice/ice_ptp_hw.h
+1
View File
@@ -704,6 +704,7 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw)
#define ICE_SMA1_MASK (ICE_SMA1_DIR_EN | ICE_SMA1_TX_EN)
#define ICE_SMA2_MASK (ICE_SMA2_UFL2_RX_DIS | ICE_SMA2_DIR_EN | \
ICE_SMA2_TX_EN)
#define ICE_SMA2_INACTIVE_MASK (ICE_SMA2_DIR_EN | ICE_SMA2_TX_EN)
#define ICE_ALL_SMA_MASK (ICE_SMA1_MASK | ICE_SMA2_MASK)
#define ICE_SMA_MIN_BIT 3