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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-05-26 11:40:24 +02:00
drm/amdgpu/mes_v12_1: add mes self test
Add mes self test to ensure that mes user queue work. V2: add pasid on amdgpu_vm_init. V3: Squash in fix non-SPX modes (Mukul) Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jack Xiao
Alex Deucher
@@ -31,6 +31,8 @@
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#include "gc/gc_11_0_0_default.h"
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#include "v12_structs.h"
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#include "mes_v12_api_def.h"
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#include "gfx_v12_1_pkt.h"
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#include "sdma_v7_1_0_pkt_open.h"
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MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes.bin");
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MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes1.bin");
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@@ -41,6 +43,7 @@ static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id);
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static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block);
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static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
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static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
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static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id);
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#define MES_EOP_SIZE 2048
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@@ -1949,10 +1952,31 @@ static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block)
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return 0;
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}
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static int mes_v12_1_late_init(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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int xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask);
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/* TODO: remove it if issue fixed. */
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if (adev->mes.enable_coop_mode)
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return 0;
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for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
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/* for COOP mode, only test master xcc. */
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if (adev->mes.enable_coop_mode &&
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adev->mes.master_xcc_ids[xcc_id] != xcc_id)
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continue;
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mes_v12_1_self_test(adev, xcc_id);
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}
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return 0;
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}
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static const struct amd_ip_funcs mes_v12_1_ip_funcs = {
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.name = "mes_v12_1",
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.early_init = mes_v12_1_early_init,
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.late_init = NULL,
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.late_init = mes_v12_1_late_init,
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.sw_init = mes_v12_1_sw_init,
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.sw_fini = mes_v12_1_sw_fini,
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.hw_init = mes_v12_1_hw_init,
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@@ -1968,3 +1992,312 @@ const struct amdgpu_ip_block_version mes_v12_1_ip_block = {
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.rev = 0,
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.funcs = &mes_v12_1_ip_funcs,
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};
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static int mes_v12_1_alloc_test_buf(struct amdgpu_device *adev,
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struct amdgpu_bo **bo, uint64_t *addr,
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void **ptr, int size)
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{
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amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
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bo, addr, ptr);
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if (!*bo) {
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dev_err(adev->dev, "failed to allocate test buffer bo\n");
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return -ENOMEM;
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}
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memset(*ptr, 0, size);
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return 0;
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}
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static int mes_v12_1_map_test_bo(struct amdgpu_device *adev,
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struct amdgpu_bo *bo, struct amdgpu_vm *vm,
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struct amdgpu_bo_va **bo_va, u64 va, int size)
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{
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struct amdgpu_sync sync;
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int r;
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r = amdgpu_map_static_csa(adev, vm, bo, bo_va, va, size);
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if (r)
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return r;
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amdgpu_sync_create(&sync);
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r = amdgpu_vm_bo_update(adev, *bo_va, false);
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if (r) {
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dev_err(adev->dev, "failed to do vm_bo_update on meta data\n");
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goto error;
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}
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amdgpu_sync_fence(&sync, (*bo_va)->last_pt_update, GFP_KERNEL);
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r = amdgpu_vm_update_pdes(adev, vm, false);
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if (r) {
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dev_err(adev->dev, "failed to update pdes on meta data\n");
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goto error;
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}
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amdgpu_sync_fence(&sync, vm->last_update, GFP_KERNEL);
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amdgpu_sync_wait(&sync, false);
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error:
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amdgpu_sync_free(&sync);
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return 0;
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}
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static int mes_v12_1_test_ring(struct amdgpu_device *adev, int xcc_id,
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u32 *queue_ptr, u64 fence_gpu_addr,
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void *fence_cpu_ptr, void *wptr_cpu_addr,
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u64 doorbell_idx, int queue_type)
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{
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volatile uint32_t *cpu_ptr = fence_cpu_ptr;
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int num_xcc = NUM_XCC(adev->gfx.xcc_mask);
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int sdma_ring_align = 0x10, compute_ring_align = 0x100;
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uint32_t tmp, xcc_offset;
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int r = 0, i, wptr = 0;
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if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {
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if (!adev->mes.enable_coop_mode) {
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WREG32_SOC15(GC, GET_INST(GC, xcc_id),
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regSCRATCH_REG0, 0xCAFEDEAD);
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} else {
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for (i = 0; i < num_xcc; i++) {
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if (adev->mes.master_xcc_ids[i] == xcc_id)
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WREG32_SOC15(GC, GET_INST(GC, i),
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regSCRATCH_REG0, 0xCAFEDEAD);
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}
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}
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xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
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queue_ptr[wptr++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
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queue_ptr[wptr++] = xcc_offset - PACKET3_SET_UCONFIG_REG_START;
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queue_ptr[wptr++] = 0xDEADBEEF;
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for (i = wptr; i < compute_ring_align; i++)
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queue_ptr[wptr++] = PACKET3(PACKET3_NOP, 0x3FFF);
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} else if (queue_type == AMDGPU_RING_TYPE_SDMA) {
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*cpu_ptr = 0xCAFEDEAD;
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queue_ptr[wptr++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
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SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
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queue_ptr[wptr++] = lower_32_bits(fence_gpu_addr);
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queue_ptr[wptr++] = upper_32_bits(fence_gpu_addr);
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queue_ptr[wptr++] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
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queue_ptr[wptr++] = 0xDEADBEEF;
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for (i = wptr; i < sdma_ring_align; i++)
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queue_ptr[wptr++] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
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wptr <<= 2;
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}
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atomic64_set((atomic64_t *)wptr_cpu_addr, wptr);
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WDOORBELL64(doorbell_idx, wptr);
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for (i = 0; i < adev->usec_timeout; i++) {
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if (queue_type == AMDGPU_RING_TYPE_SDMA) {
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tmp = le32_to_cpu(*cpu_ptr);
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} else {
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if (!adev->mes.enable_coop_mode) {
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tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
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regSCRATCH_REG0);
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} else {
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for (i = 0; i < num_xcc; i++) {
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if (xcc_id != adev->mes.master_xcc_ids[i])
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continue;
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tmp = RREG32_SOC15(GC, GET_INST(GC, i),
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regSCRATCH_REG0);
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if (tmp != 0xDEADBEEF)
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break;
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}
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}
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}
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if (tmp == 0xDEADBEEF)
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break;
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if (amdgpu_emu_mode == 1)
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msleep(1);
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else
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udelay(1);
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}
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if (i >= adev->usec_timeout) {
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dev_err(adev->dev, "xcc%d: mes self test (%s) failed\n", xcc_id,
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queue_type == AMDGPU_RING_TYPE_SDMA ? "sdma" : "compute");
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while (halt_if_hws_hang)
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schedule();
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r = -ETIMEDOUT;
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} else {
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dev_info(adev->dev, "xcc%d: mes self test (%s) pass\n", xcc_id,
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queue_type == AMDGPU_RING_TYPE_SDMA ? "sdma" : "compute");
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}
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return r;
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}
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#define USER_CTX_SIZE (PAGE_SIZE * 2)
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#define USER_CTX_VA AMDGPU_VA_RESERVED_BOTTOM
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#define RING_OFFSET(addr) ((addr))
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#define EOP_OFFSET(addr) ((addr) + PAGE_SIZE)
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#define WPTR_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64))
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#define RPTR_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64) * 2)
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#define FENCE_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64) * 3)
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static int mes_v12_1_test_queue(struct amdgpu_device *adev, int xcc_id,
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int pasid, struct amdgpu_vm *vm, u64 meta_gpu_addr,
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u64 queue_gpu_addr, void *ctx_ptr, int queue_type)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
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struct amdgpu_mqd *mqd_mgr = &adev->mqds[queue_type];
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struct amdgpu_mqd_prop mqd_prop = {0};
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struct mes_add_queue_input add_queue = {0};
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struct mes_remove_queue_input remove_queue = {0};
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struct amdgpu_bo *mqd_bo = NULL;
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int num_xcc = NUM_XCC(adev->gfx.xcc_mask);
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int i, r, off, mqd_size, mqd_count = 1;
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void *mqd_ptr = NULL;
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u64 mqd_gpu_addr, doorbell_idx;
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/* extra one page size padding for mes fw */
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mqd_size = mqd_mgr->mqd_size + PAGE_SIZE;
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if (queue_type == AMDGPU_RING_TYPE_SDMA) {
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doorbell_idx = adev->mes.db_start_dw_offset + \
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adev->doorbell_index.sdma_engine[0];
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} else {
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doorbell_idx = adev->mes.db_start_dw_offset + \
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adev->doorbell_index.userqueue_start;
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}
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if (adev->mes.enable_coop_mode &&
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queue_type == AMDGPU_RING_TYPE_COMPUTE) {
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for (i = 0, mqd_count = 0; i < num_xcc; i++) {
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if (adev->mes.master_xcc_ids[i] == xcc_id)
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mqd_count++;
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}
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mqd_size *= mqd_count;
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}
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r = mes_v12_1_alloc_test_buf(adev, &mqd_bo, &mqd_gpu_addr,
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&mqd_ptr, mqd_size * mqd_count);
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if (r < 0)
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return r;
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mqd_prop.mqd_gpu_addr = mqd_gpu_addr;
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mqd_prop.hqd_base_gpu_addr = RING_OFFSET(USER_CTX_VA);
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mqd_prop.eop_gpu_addr = EOP_OFFSET(USER_CTX_VA);
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mqd_prop.wptr_gpu_addr = WPTR_OFFSET(USER_CTX_VA);
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mqd_prop.rptr_gpu_addr = RPTR_OFFSET(USER_CTX_VA);
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mqd_prop.doorbell_index = doorbell_idx;
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mqd_prop.queue_size = PAGE_SIZE;
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mqd_prop.mqd_stride_size = mqd_size;
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mqd_prop.use_doorbell = true;
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mqd_prop.hqd_active = false;
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mqd_mgr->init_mqd(adev, mqd_ptr, &mqd_prop);
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if (mqd_count > 1) {
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for (i = 1; i < mqd_count; i++) {
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off = mqd_size * i;
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mqd_prop.mqd_gpu_addr = mqd_gpu_addr + off;
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mqd_mgr->init_mqd(adev, (char *)mqd_ptr + off,
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&mqd_prop);
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}
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}
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add_queue.xcc_id = xcc_id;
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add_queue.process_id = pasid;
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add_queue.page_table_base_addr = adev->vm_manager.vram_base_offset +
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amdgpu_bo_gpu_offset(vm->root.bo) - adev->gmc.vram_start;
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add_queue.process_va_start = 0;
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add_queue.process_va_end = adev->vm_manager.max_pfn - 1;
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add_queue.process_context_addr = meta_gpu_addr;
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add_queue.gang_context_addr = meta_gpu_addr + AMDGPU_MES_PROC_CTX_SIZE;
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add_queue.doorbell_offset = doorbell_idx;
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add_queue.mqd_addr = mqd_gpu_addr;
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add_queue.wptr_addr = mqd_prop.wptr_gpu_addr;
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add_queue.wptr_mc_addr = WPTR_OFFSET(queue_gpu_addr);
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add_queue.queue_type = queue_type;
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add_queue.vm_cntx_cntl = hub->vm_cntx_cntl;
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r = mes_v12_1_add_hw_queue(&adev->mes, &add_queue);
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if (r)
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goto error;
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mes_v12_1_test_ring(adev, xcc_id, (u32 *)RING_OFFSET((char *)ctx_ptr),
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FENCE_OFFSET(USER_CTX_VA),
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FENCE_OFFSET((char *)ctx_ptr),
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WPTR_OFFSET((char *)ctx_ptr),
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doorbell_idx, queue_type);
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remove_queue.xcc_id = xcc_id;
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remove_queue.doorbell_offset = doorbell_idx;
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remove_queue.gang_context_addr = add_queue.gang_context_addr;
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r = mes_v12_1_remove_hw_queue(&adev->mes, &remove_queue);
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error:
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amdgpu_bo_free_kernel(&mqd_bo, &mqd_gpu_addr, &mqd_ptr);
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return r;
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}
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static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id)
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{
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int queue_types[] = { AMDGPU_RING_TYPE_COMPUTE,
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/* AMDGPU_RING_TYPE_SDMA */ };
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struct amdgpu_bo_va *bo_va = NULL;
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struct amdgpu_vm *vm = NULL;
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struct amdgpu_bo *meta_bo = NULL, *ctx_bo = NULL;
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void *meta_ptr = NULL, *ctx_ptr = NULL;
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u64 meta_gpu_addr, ctx_gpu_addr;
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int size, i, r, pasid;;
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pasid = amdgpu_pasid_alloc(16);
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if (pasid < 0)
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pasid = 0;
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size = AMDGPU_MES_PROC_CTX_SIZE + AMDGPU_MES_GANG_CTX_SIZE;
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r = mes_v12_1_alloc_test_buf(adev, &meta_bo, &meta_gpu_addr,
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&meta_ptr, size);
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if (r < 0)
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goto err2;
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r = mes_v12_1_alloc_test_buf(adev, &ctx_bo, &ctx_gpu_addr,
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&ctx_ptr, USER_CTX_SIZE);
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if (r < 0)
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goto err2;
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vm = kzalloc(sizeof(*vm), GFP_KERNEL);
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if (!vm) {
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r = -ENOMEM;
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goto err2;
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}
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r = amdgpu_vm_init(adev, vm, -1, pasid);
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if (r)
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goto err1;
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r = mes_v12_1_map_test_bo(adev, ctx_bo, vm, &bo_va,
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USER_CTX_VA, USER_CTX_SIZE);
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if (r)
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goto err0;
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for (i = 0; i < ARRAY_SIZE(queue_types); i++) {
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memset(ctx_ptr, 0, USER_CTX_SIZE);
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r = mes_v12_1_test_queue(adev, xcc_id, pasid, vm, meta_gpu_addr,
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ctx_gpu_addr, ctx_ptr, queue_types[i]);
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if (r)
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break;
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}
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amdgpu_unmap_static_csa(adev, vm, ctx_bo, bo_va, USER_CTX_VA);
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err0:
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amdgpu_vm_fini(adev, vm);
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err1:
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kfree(vm);
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err2:
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amdgpu_bo_free_kernel(&meta_bo, &meta_gpu_addr, &meta_ptr);
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amdgpu_bo_free_kernel(&ctx_bo, &ctx_gpu_addr, &ctx_ptr);
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amdgpu_pasid_free(pasid);
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return r;
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}
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