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coresight: etm4x: Add context synchronization before enabling trace
According to the software usage PKLXF in Arm ARM (ARM DDI 0487 L.a), a
Context synchronization event is required before enabling the trace
unit.
An ISB is added to meet this requirement, particularly for guarding the
operations in the flow:
etm4x_allow_trace()
`> kvm_tracing_set_el1_configuration()
`> write_sysreg_s(trfcr_while_in_guest, SYS_TRFCR_EL12)
Improved the barrier comments to provide more accurate information.
Fixes: 1ab3bb9df5 ("coresight: etm4x: Add necessary synchronization for sysreg access")
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Yeoreun Yun <yeoreum.yun@arm.com>
Tested-by: James Clark <james.clark@linaro.org>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20251111-arm_coresight_power_management_fix-v6-5-f55553b6c8b3@arm.com
This commit is contained in:
committed by
Suzuki K Poulose
parent
4dc4e22f95
commit
64eb04ae54
@@ -446,10 +446,24 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata)
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etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
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etm4x_allow_trace(drvdata);
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/*
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* According to software usage PKLXF in Arm ARM (ARM DDI 0487 L.a),
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* execute a Context synchronization event to guarantee the trace unit
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* will observe the new values of the System registers.
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*/
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if (!csa->io_mem)
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isb();
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/* Enable the trace unit */
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etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
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/* Synchronize the register updates for sysreg access */
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/*
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* As recommended by section 4.3.7 ("Synchronization when using system
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* instructions to progrom the trace unit") of ARM IHI 0064H.b, the
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* self-hosted trace analyzer must perform a Context synchronization
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* event between writing to the TRCPRGCTLR and reading the TRCSTATR.
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*/
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if (!csa->io_mem)
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isb();
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@@ -931,11 +945,16 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata)
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*/
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etm4x_prohibit_trace(drvdata);
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/*
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* Make sure everything completes before disabling, as recommended
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* by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
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* SSTATUS") of ARM IHI 0064D
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* Prevent being speculative at the point of disabling the trace unit,
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* as recommended by section 7.3.77 ("TRCVICTLR, ViewInst Main Control
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* Register, SSTATUS") of ARM IHI 0064D
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*/
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dsb(sy);
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/*
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* According to software usage VKHHY in Arm ARM (ARM DDI 0487 L.a),
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* execute a Context synchronization event to guarantee no new
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* program-flow trace is generated.
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*/
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isb();
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/* Trace synchronization barrier, is a nop if not supported */
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tsb_csync();
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