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arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery

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I2C bus recovery need a pinmux and gpio. So i2c driver can switch
gpio mode to toggle scl to recovery bus.

Add pinctrl-single node to every i2c bus on fsl-ls2160 layerscape
platform.

Signed-off-by: Carlos Song <carlos.song@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Carlos Song
2024-03-28 14:14:19 +08:00
committed by Shawn Guo
parent 44b305a2de
commit 8a1365c7bb
1 changed files with 106 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+106 -2
View File
@@ -748,7 +748,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c0_scl>;
pinctrl-1 = <&i2c0_scl_gpio>;
scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -761,6 +764,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c1_scl>;
pinctrl-1 = <&i2c1_scl_gpio>;
scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -773,6 +780,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c2_scl>;
pinctrl-1 = <&i2c2_scl_gpio>;
scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -785,6 +796,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c3_scl>;
pinctrl-1 = <&i2c3_scl_gpio>;
scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -797,7 +812,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c4_scl>;
pinctrl-1 = <&i2c4_scl_gpio>;
scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -810,6 +828,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c5_scl>;
pinctrl-1 = <&i2c5_scl_gpio>;
scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -822,6 +844,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c6_scl>;
pinctrl-1 = <&i2c6_scl_gpio>;
scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -834,6 +860,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c7_scl>;
pinctrl-1 = <&i2c7_scl_gpio>;
scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -1669,6 +1699,80 @@
};
};
pinmux_i2crv: pinmux@70010012c {
compatible = "pinctrl-single";
reg = <0x00000007 0x0010012c 0x0 0xc>;
#address-cells = <2>;
#size-cells = <2>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7>;
i2c1_scl: i2c1-scl-pins {
pinctrl-single,bits = <0x0 0 0x7>;
};
i2c1_scl_gpio: i2c1-scl-gpio-pins {
pinctrl-single,bits = <0x0 0x1 0x7>;
};
i2c2_scl: i2c2-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
};
i2c2_scl_gpio: i2c2-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
};
i2c3_scl: i2c3-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 6)>;
};
i2c3_scl_gpio: i2c3-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
};
i2c4_scl: i2c4-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 9)>;
};
i2c4_scl_gpio: i2c4-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
};
i2c5_scl: i2c5-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 12)>;
};
i2c5_scl_gpio: i2c5-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
};
i2c6_scl: i2c6-scl-pins {
pinctrl-single,bits = <0x4 0x2 0x7>;
};
i2c6_scl_gpio: i2c6-scl-gpio-pins {
pinctrl-single,bits = <0x4 0x1 0x7>;
};
i2c7_scl: i2c7-scl-pins {
pinctrl-single,bits = <0x4 0x2 0x7>;
};
i2c7_scl_gpio: i2c7-scl-gpio-pins {
pinctrl-single,bits = <0x4 0x1 0x7>;
};
i2c0_scl: i2c0-scl-pins {
pinctrl-single,bits = <0x8 0 (0x7 << 10)>;
};
i2c0_scl_gpio: i2c0-scl-gpio-pins {
pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
};
};
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>,