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arm64: dts: rockchip: add rk3588 PCIe2 support
Add all three PCIe2 IP blocks to the RK3588 DT. Note, that RK3588 also has two PCIe3 IP blocks, that will be handled separately. Co-developed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-neu6a, 6b Reviewed-by: Jagan Teki <jagan@edgeble.ai> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230731165723.53069-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Sebastian Reichel
committed by
Heiko Stuebner
Heiko Stuebner
parent
eddf730297
commit
8d81b77f4c
@@ -187,6 +187,57 @@
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};
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};
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pcie2x1l0: pcie@fe170000 {
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compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
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bus-range = <0x20 0x2f>;
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clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
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<&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
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<&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux", "pipe";
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device_type = "pci";
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interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
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<0 0 0 2 &pcie2x1l0_intc 1>,
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<0 0 0 3 &pcie2x1l0_intc 2>,
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<0 0 0 4 &pcie2x1l0_intc 3>;
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linux,pci-domain = <2>;
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max-link-speed = <2>;
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msi-map = <0x2000 &its0 0x2000 0x1000>;
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num-lanes = <1>;
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phys = <&combphy1_ps PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PCIE>;
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ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
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<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
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<0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
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reg = <0xa 0x40800000 0x0 0x00400000>,
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<0x0 0xfe170000 0x0 0x00010000>,
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<0x0 0xf2000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
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reset-names = "pwr", "pipe";
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#address-cells = <3>;
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#size-cells = <2>;
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status = "disabled";
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pcie2x1l0_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
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};
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};
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gmac0: ethernet@fe1b0000 {
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compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
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reg = <0x0 0xfe1b0000 0x0 0x10000>;
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@@ -1227,6 +1227,108 @@
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reg = <0x0 0xfdf82200 0x0 0x20>;
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};
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pcie2x1l1: pcie@fe180000 {
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compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
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bus-range = <0x30 0x3f>;
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clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
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<&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
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<&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux", "pipe";
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device_type = "pci";
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interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
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<0 0 0 2 &pcie2x1l1_intc 1>,
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<0 0 0 3 &pcie2x1l1_intc 2>,
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<0 0 0 4 &pcie2x1l1_intc 3>;
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linux,pci-domain = <3>;
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max-link-speed = <2>;
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msi-map = <0x3000 &its0 0x3000 0x1000>;
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num-lanes = <1>;
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phys = <&combphy2_psu PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PCIE>;
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ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
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<0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
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<0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
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reg = <0xa 0x40c00000 0x0 0x00400000>,
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<0x0 0xfe180000 0x0 0x00010000>,
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<0x0 0xf3000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
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reset-names = "pwr", "pipe";
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#address-cells = <3>;
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#size-cells = <2>;
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status = "disabled";
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pcie2x1l1_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
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};
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};
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pcie2x1l2: pcie@fe190000 {
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compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
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bus-range = <0x40 0x4f>;
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clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
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<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
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<&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux", "pipe";
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device_type = "pci";
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interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
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<0 0 0 2 &pcie2x1l2_intc 1>,
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<0 0 0 3 &pcie2x1l2_intc 2>,
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<0 0 0 4 &pcie2x1l2_intc 3>;
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linux,pci-domain = <4>;
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max-link-speed = <2>;
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msi-map = <0x4000 &its0 0x4000 0x1000>;
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num-lanes = <1>;
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phys = <&combphy0_ps PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PCIE>;
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ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
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<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
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<0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
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reg = <0xa 0x41000000 0x0 0x00400000>,
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<0x0 0xfe190000 0x0 0x00010000>,
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<0x0 0xf4000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
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reset-names = "pwr", "pipe";
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#address-cells = <3>;
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#size-cells = <2>;
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status = "disabled";
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pcie2x1l2_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
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};
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};
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gmac1: ethernet@fe1c0000 {
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compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
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reg = <0x0 0xfe1c0000 0x0 0x10000>;
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