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platform/x86/intel/tpmi: Use 32 bit aligned address for debugfs mem write

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The memory write feature supports 32-bit writes to any TPMI offset.
However, future hardware generations may not allow writes to non-32-bit
aligned addresses due to hardware optimizations.

Since all TPMI addresses are 64-bit aligned and correspond to 64-bit
registers, enforce 32-bit alignment for write operations.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Link: https://patch.msgid.link/20260326182446.3478672-1-srinivas.pandruvada@linux.intel.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
This commit is contained in:
Srinivas Pandruvada
2026-03-31 18:45:11 +03:00
committed by Ilpo Järvinen
parent 9ec6bf62cf
commit 8e0a2fc68e
1 changed files with 4 additions and 0 deletions
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drivers/platform/x86/intel/vsec_tpmi.c
+4
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@@ -46,6 +46,7 @@
* provided by the Intel VSEC driver.
*/
#include <linux/align.h>
#include <linux/auxiliary_bus.h>
#include <linux/bitfield.h>
#include <linux/debugfs.h>
@@ -479,6 +480,9 @@ static ssize_t mem_write(struct file *file, const char __user *userbuf, size_t l
addr = array[2];
value = array[3];
if (!IS_ALIGNED(addr, sizeof(u32)))
return -EINVAL;
if (punit >= pfs->pfs_header.num_entries) {
ret = -EINVAL;
goto exit_write;