averello/linux-stable-mirror
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2026-03-03 18:28:01 +01:00
Code Issues Packages Projects Releases Wiki Activity

clk: stm32: stm32-core: convert from round_rate() to determine_rate()

Browse Source 
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Reviewed-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
This commit is contained in:
Brian Masney
2025-08-11 11:18:50 -04:00
parent 028b0eb1c9
commit cd1cb38836
1 changed files with 18 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
drivers/clk/stm32/clk-stm32-core.c
View File

@@ -351,14 +351,14 @@ static int clk_stm32_divider_set_rate(struct clk_hw *hw, unsigned long rate,
return ret;
}
static long clk_stm32_divider_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
static int clk_stm32_divider_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_stm32_div *div = to_clk_stm32_divider(hw);
const struct stm32_div_cfg *divider;
if (div->div_id == NO_STM32_DIV)
return rate;
return 0;
divider = &div->clock_data->dividers[div->div_id];
@@ -369,14 +369,22 @@ static long clk_stm32_divider_round_rate(struct clk_hw *hw, unsigned long rate,
val = readl(div->base + divider->offset) >> divider->shift;
val &= clk_div_mask(divider->width);
return divider_ro_round_rate(hw, rate, prate, divider->table,
divider->width, divider->flags,
val);
req->rate = divider_ro_round_rate(hw, req->rate,
&req->best_parent_rate,
divider->table,
divider->width,
divider->flags, val);
return 0;
}
return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
rate, prate, divider->table,
divider->width, divider->flags);
req->rate = divider_round_rate_parent(hw, clk_hw_get_parent(hw),
req->rate,
&req->best_parent_rate,
divider->table,
divider->width, divider->flags);
return 0;
}
static unsigned long clk_stm32_divider_recalc_rate(struct clk_hw *hw,
@@ -392,7 +400,7 @@ static unsigned long clk_stm32_divider_recalc_rate(struct clk_hw *hw,
const struct clk_ops clk_stm32_divider_ops = {
.recalc_rate = clk_stm32_divider_recalc_rate,
.round_rate = clk_stm32_divider_round_rate,
.determine_rate = clk_stm32_divider_determine_rate,
.set_rate = clk_stm32_divider_set_rate,
};