From db9c882f83d3f3e08069f52d0d2ebf9d131c9ae4 Mon Sep 17 00:00:00 2001 From: Dyllan Kobal Date: Tue, 23 Jun 2026 00:58:04 +0000 Subject: [PATCH] drm/amd/display: fix wrong register field in dccg35_set_hdmistreamclk_src_new dccg35_set_hdmistreamclk_src_new() updates HDMISTREAMCLK_CNTL but passes DPSTREAMCLK0_SRC_SEL as the field identifier in the second REG_UPDATE_2 slot. The current behavior is harmless on DCN3.5 because both fields share the same bit layout, but it is still incorrect and could break on future hardware revisions. Fixes: d36771a03412 ("drm/amd/display: Add DCCG DIO, HPO, OPP, and OPTC support for FRL") Signed-off-by: Dyllan Kobal Reviewed-by: George Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 5c9ef30b5416..71903a6c63a0 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -572,7 +572,7 @@ static void dccg35_set_hdmistreamclk_src_new( case 0: REG_UPDATE_2(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, (src == HDMI_STREAM_REFCLK) ? 0 : 1, - DPSTREAMCLK0_SRC_SEL, + HDMISTREAMCLK0_SRC_SEL, (src == HDMI_STREAM_REFCLK) ? 0 : src); break; default: