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net: phy: Rename Airoha common BuckPBus register accessors
Rename the BuckPBus register accessors functions present in air_phy_lib and their calls in air_en8811h driver, so all exported functions start with the same prefix. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Link: https://patch.msgid.link/20260526-add-airoha-an8801-support-v5-4-01aea8dee69b@collabora.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Louis-Alexis Eyraud
committed by
Jakub Kicinski
Jakub Kicinski
parent
5226bb6634
commit
e08f0ea6da
@@ -287,8 +287,8 @@ static int en8811h_wait_mcu_ready(struct phy_device *phydev)
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{
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int ret, reg_value;
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ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
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EN8811H_FW_CTRL_1_FINISH);
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ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
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EN8811H_FW_CTRL_1_FINISH);
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if (ret)
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return ret;
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@@ -313,28 +313,29 @@ static int an8811hb_check_crc(struct phy_device *phydev, u32 set1,
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int ret;
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/* Configure CRC */
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ret = air_buckpbus_reg_modify(phydev, set1,
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AN8811HB_CRC_RD_EN,
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AN8811HB_CRC_RD_EN);
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ret = air_phy_buckpbus_reg_modify(phydev, set1,
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AN8811HB_CRC_RD_EN,
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AN8811HB_CRC_RD_EN);
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if (ret < 0)
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return ret;
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air_buckpbus_reg_read(phydev, set1, &pbus_value);
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air_phy_buckpbus_reg_read(phydev, set1, &pbus_value);
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do {
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msleep(300);
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air_buckpbus_reg_read(phydev, mon2, &pbus_value);
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air_phy_buckpbus_reg_read(phydev, mon2, &pbus_value);
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/* We do not know what errors this check is supposed
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* catch or what to do about a failure. So print the
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* result and continue like the vendor driver does.
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*/
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if (pbus_value & AN8811HB_CRC_ST) {
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air_buckpbus_reg_read(phydev, mon3, &pbus_value);
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air_phy_buckpbus_reg_read(phydev, mon3, &pbus_value);
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phydev_dbg(phydev, "CRC Check %s!\n",
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pbus_value & AN8811HB_CRC_CHECK_PASS ?
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"PASS" : "FAIL");
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return air_buckpbus_reg_modify(phydev, set1,
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AN8811HB_CRC_RD_EN, 0);
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return air_phy_buckpbus_reg_modify(phydev, set1,
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AN8811HB_CRC_RD_EN,
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0);
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}
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} while (--retry);
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@@ -346,8 +347,8 @@ static void en8811h_print_fw_version(struct phy_device *phydev)
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{
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struct en8811h_priv *priv = phydev->priv;
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air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
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&priv->firmware_version);
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air_phy_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
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&priv->firmware_version);
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phydev_info(phydev, "MD32 firmware version: %08x\n",
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priv->firmware_version);
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}
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@@ -372,8 +373,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev)
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{
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int ret;
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ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
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EN8811H_FW_CTRL_1_START);
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ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
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EN8811H_FW_CTRL_1_START);
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if (ret < 0)
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return ret;
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@@ -414,14 +415,14 @@ static int en8811h_load_firmware(struct phy_device *phydev)
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if (ret < 0)
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goto en8811h_load_firmware_rel1;
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ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
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EN8811H_FW_CTRL_1_START);
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ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
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EN8811H_FW_CTRL_1_START);
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if (ret < 0)
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goto en8811h_load_firmware_out;
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ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
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EN8811H_FW_CTRL_2_LOADING,
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EN8811H_FW_CTRL_2_LOADING);
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ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
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EN8811H_FW_CTRL_2_LOADING,
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EN8811H_FW_CTRL_2_LOADING);
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if (ret < 0)
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goto en8811h_load_firmware_out;
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@@ -433,8 +434,8 @@ static int en8811h_load_firmware(struct phy_device *phydev)
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if (ret < 0)
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goto en8811h_load_firmware_out;
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ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
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EN8811H_FW_CTRL_2_LOADING, 0);
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ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
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EN8811H_FW_CTRL_2_LOADING, 0);
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if (ret < 0)
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goto en8811h_load_firmware_out;
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@@ -460,8 +461,8 @@ static int en8811h_restart_mcu(struct phy_device *phydev)
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{
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int ret;
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ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
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EN8811H_FW_CTRL_1_START);
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ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
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EN8811H_FW_CTRL_1_START);
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if (ret < 0)
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return ret;
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@@ -755,7 +756,7 @@ static unsigned long an8811hb_clk_recalc_rate(struct clk_hw *hw,
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u32 pbus_value;
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int ret;
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ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
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ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
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if (ret < 0)
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return ret;
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@@ -767,9 +768,9 @@ static int an8811hb_clk_enable(struct clk_hw *hw)
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struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
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struct phy_device *phydev = priv->phydev;
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return air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
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AN8811HB_CLK_DRV_CKO_MASK,
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AN8811HB_CLK_DRV_CKO_MASK);
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return air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
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AN8811HB_CLK_DRV_CKO_MASK,
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AN8811HB_CLK_DRV_CKO_MASK);
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}
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static void an8811hb_clk_disable(struct clk_hw *hw)
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@@ -777,8 +778,8 @@ static void an8811hb_clk_disable(struct clk_hw *hw)
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struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
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struct phy_device *phydev = priv->phydev;
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air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
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AN8811HB_CLK_DRV_CKO_MASK, 0);
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air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
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AN8811HB_CLK_DRV_CKO_MASK, 0);
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}
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static int an8811hb_clk_is_enabled(struct clk_hw *hw)
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@@ -788,7 +789,7 @@ static int an8811hb_clk_is_enabled(struct clk_hw *hw)
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u32 pbus_value;
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int ret;
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ret = air_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
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ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
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if (ret < 0)
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return ret;
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@@ -854,7 +855,7 @@ static unsigned long en8811h_clk_recalc_rate(struct clk_hw *hw,
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u32 pbus_value;
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int ret;
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ret = air_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
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ret = air_phy_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
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if (ret < 0)
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return ret;
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@@ -866,9 +867,9 @@ static int en8811h_clk_enable(struct clk_hw *hw)
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struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
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struct phy_device *phydev = priv->phydev;
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return air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
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EN8811H_CLK_CGM_CKO,
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EN8811H_CLK_CGM_CKO);
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return air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
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EN8811H_CLK_CGM_CKO,
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EN8811H_CLK_CGM_CKO);
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}
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static void en8811h_clk_disable(struct clk_hw *hw)
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@@ -876,8 +877,8 @@ static void en8811h_clk_disable(struct clk_hw *hw)
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struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
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struct phy_device *phydev = priv->phydev;
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air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
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EN8811H_CLK_CGM_CKO, 0);
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air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
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EN8811H_CLK_CGM_CKO, 0);
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}
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static int en8811h_clk_is_enabled(struct clk_hw *hw)
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@@ -887,7 +888,7 @@ static int en8811h_clk_is_enabled(struct clk_hw *hw)
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u32 pbus_value;
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int ret;
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ret = air_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
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ret = air_phy_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
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if (ret < 0)
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return ret;
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@@ -998,9 +999,9 @@ static int an8811hb_probe(struct phy_device *phydev)
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return ret;
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/* Configure led gpio pins as output */
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ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
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AN8811HB_GPIO_OUTPUT_345,
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AN8811HB_GPIO_OUTPUT_345);
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ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
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AN8811HB_GPIO_OUTPUT_345,
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AN8811HB_GPIO_OUTPUT_345);
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if (ret < 0)
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return ret;
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@@ -1039,9 +1040,9 @@ static int en8811h_probe(struct phy_device *phydev)
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return ret;
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/* Configure led gpio pins as output */
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ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
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EN8811H_GPIO_OUTPUT_345,
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EN8811H_GPIO_OUTPUT_345);
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ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
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EN8811H_GPIO_OUTPUT_345,
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EN8811H_GPIO_OUTPUT_345);
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if (ret < 0)
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return ret;
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@@ -1061,9 +1062,9 @@ static int an8811hb_config_serdes_polarity(struct phy_device *phydev)
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return ret;
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if (pol == PHY_POL_NORMAL)
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pbus_value |= AN8811HB_RX_POLARITY_NORMAL;
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ret = air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
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AN8811HB_RX_POLARITY_NORMAL,
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pbus_value);
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ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
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AN8811HB_RX_POLARITY_NORMAL,
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pbus_value);
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if (ret < 0)
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return ret;
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@@ -1074,9 +1075,9 @@ static int an8811hb_config_serdes_polarity(struct phy_device *phydev)
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pbus_value = 0;
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if (pol == PHY_POL_NORMAL)
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pbus_value |= AN8811HB_TX_POLARITY_NORMAL;
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return air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
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AN8811HB_TX_POLARITY_NORMAL,
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pbus_value);
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return air_phy_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
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AN8811HB_TX_POLARITY_NORMAL,
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pbus_value);
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}
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static int en8811h_config_serdes_polarity(struct phy_device *phydev)
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@@ -1110,9 +1111,10 @@ static int en8811h_config_serdes_polarity(struct phy_device *phydev)
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if (pol == PHY_POL_NORMAL)
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pbus_value |= EN8811H_POLARITY_TX_NORMAL;
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return air_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
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EN8811H_POLARITY_RX_REVERSE |
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EN8811H_POLARITY_TX_NORMAL, pbus_value);
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return air_phy_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
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EN8811H_POLARITY_RX_REVERSE |
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EN8811H_POLARITY_TX_NORMAL,
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pbus_value);
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}
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static int an8811hb_config_init(struct phy_device *phydev)
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@@ -1264,8 +1266,8 @@ static int en8811h_read_status(struct phy_device *phydev)
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val & MDIO_AN_10GBT_STAT_LP2_5G);
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} else {
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/* Get link partner 2.5GBASE-T ability from vendor register */
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ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
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&pbus_value);
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ret = air_phy_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
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&pbus_value);
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if (ret < 0)
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return ret;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
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@@ -137,8 +137,8 @@ static int __air_buckpbus_reg_modify(struct phy_device *phydev,
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return 0;
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}
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int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
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u32 *pbus_data)
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int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
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u32 *pbus_data)
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{
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int saved_page;
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int ret = 0;
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@@ -154,10 +154,10 @@ int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
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return phy_restore_page(phydev, saved_page, ret);
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}
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EXPORT_SYMBOL_GPL(air_buckpbus_reg_read);
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EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_read);
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int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
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u32 pbus_data)
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int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
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u32 pbus_data)
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{
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int saved_page;
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int ret = 0;
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@@ -174,10 +174,10 @@ int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
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return phy_restore_page(phydev, saved_page, ret);
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}
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EXPORT_SYMBOL_GPL(air_buckpbus_reg_write);
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EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_write);
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int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
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u32 mask, u32 set)
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int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
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u32 mask, u32 set)
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{
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int saved_page;
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int ret = 0;
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@@ -194,7 +194,7 @@ int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
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return phy_restore_page(phydev, saved_page, ret);
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}
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EXPORT_SYMBOL_GPL(air_buckpbus_reg_modify);
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EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_modify);
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int air_phy_read_page(struct phy_device *phydev)
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{
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@@ -27,12 +27,12 @@
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#define AIR_BPBUS_RD_DATA_HIGH 0x17
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#define AIR_BPBUS_RD_DATA_LOW 0x18
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int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
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u32 mask, u32 set);
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int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
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u32 *pbus_data);
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int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
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u32 pbus_data);
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int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
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u32 mask, u32 set);
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int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
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u32 *pbus_data);
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int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
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u32 pbus_data);
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int air_phy_read_page(struct phy_device *phydev);
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int air_phy_write_page(struct phy_device *phydev, int page);
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