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399 Commits

Author SHA1 Message Date
Alex Deucher
9626d3af3c drm/amdgpu: Add additional DCE6 SCL registers 
[ Upstream commit 507296328b ]

Fixes: 102b2f587a ("drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2)")
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
 2025-10-19 16:33:42 +02:00
Harish Kasiviswanathan
452807a863 drm/amdgpu: Set snoop bit for SDMA for MI series 
[ Upstream commit 3394b1f76d ]

SDMA writes has to probe invalidate RW lines. Set snoop bit in mmhub for
this to happen.

v2: Missed a few mmhub_v9_4. Added now.
v3: Calculate hub offset once since it doesn't change inside the loop
    Modified function names based on review comments.

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
 2025-05-29 11:02:52 +02:00
Mario Limonciello
be51376b1f drm/amd: Add some missing straps from NBIO 7.11.0 
commit 902fbbf429 upstream.

Earlier ASICs have strap information exported, and this is missing
for NBIO 7.11.0.

Cc: stable@vger.kernel.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Fixes: ca8c68142a ("drm/amdgpu: add nbio 7.11 registers")
Link: https://lore.kernel.org/r/20241118174611.10700-1-mario.limonciello@amd.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2024-12-09 10:41:14 +01:00
Remington Brasga
3834ce3600 drm/amdgpu/uvd4: fix mask and shift definitions 
A few define's are listed twice with different, incorrect values.
This fix sets them appropriately.

Signed-off-by: Remington Brasga <rbrasga@uci.edu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-08-13 10:26:48 -04:00
David Belanger
666f14cab2 drm/amdgpu: Fix atomics on GFX12 
If PCIe supports atomics, configure register to prevent DF from
breaking atomics in separate load/store operations.

Signed-off-by: David Belanger <david.belanger@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-07-23 17:33:17 -04:00
Aurabindo Pillai
ad89e904e3 drm/amd: Add some missing register definitions 
Add some register offsets that are required for Display DCC on DCN401

Fixes: 2d072b4456 ("drm/amd: Add reg definitions for DCN401 DCC")
Reported-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-06-27 17:32:17 -04:00
Aurabindo Pillai
2d072b4456 drm/amd: Add reg definitions for DCN401 DCC 
[WHAT]
Add the necessary register definitions to enable DCC on DCN4x

Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-06-27 17:10:38 -04:00
Alex Deucher
b592d01df6 drm/amdgpu: update gc_12_0_0 headers 
Add some additional registers.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-06-05 11:03:10 -04:00
Rodrigo Siqueira
d0a6d85072 drm/amd/display: Add missing registers for DCN401 
Add some additional registers.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-29 14:40:39 -04:00
Sunil Khatri
eb14b8f505 drm/amdgpu: Add missing offsets in gc_11_0_0_offset.h 
IB1 registers:
regCP_IB1_CMD_BUFSZ
regCP_IB1_BASE_LO
regCP_IB1_BASE_HI
regCP_IB1_BUFSZ
regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR

Above registers are part of the asic but not of
the offset file for gc_11_0_0_offset.h and hence
adding them.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-23 15:13:34 -04:00
Kenneth Feng
e7d1f1162b drm/amd/amdgpu: add thm 14.0.2 header file 
add thm 14.0.2 header file

v2: add license, update to latest changes (Alex)

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
 2024-05-20 16:20:26 -04:00
Hawking Zhang
3a99045c56 drm/amdgpu: Add mmhub v4_1_0 ip headers (v4) 
v1: Add mmhub v4_1_0 register offset and shift masks
    header files. (Hawking)
v2: Update mmhub v4_1_0 register offset and shift masks
    header files to RE2. (Likun)
v3: Update mmhub v4_1_0 register offset and shift masks
    header files to RE2.5 (Likun)
v4: Clean up mmhub v4_1_0 ip headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-30 09:51:27 -04:00
Hawking Zhang
db4f0d544e drm/amdgpu: Add gc v12_0_0 ip headers (v4) 
v1: Add gc v12_0_0 register offset and shift masks
    header files. (Hawking)
v2: Update gc v12_0_0 register offset and shift masks
    header files to LSD version. (Likun)
v3: Update gc v12_0_0 register offset and shift masks
    header files to RE3 version. (Likun)
v4: Updates (Alex)
v5: updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-30 09:46:29 -04:00
Aurabindo Pillai
59a0c03a50 drm/amd: Add DCN401 related register definitions 
Update register headers.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-26 17:23:08 -04:00
Rodrigo Siqueira
5e66f6eaa2 drm/amd/display: Add some missing HDMI registers for DCN3x 
This commit add some missing HDMI control registers to DCN3x.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-26 17:22:42 -04:00
Rodrigo Siqueira
71dfa617ea drm/amd/display: Add missing debug registers for DCN2/3/3.1 
This commit add some missing debug registers for DPCS and RDPC debug.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-26 17:22:40 -04:00
Sunil Khatri
c395dbb68b drm/amdgpu: add support of gfx10 register dump 
Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-26 17:22:39 -04:00
Sunil Khatri
cba9b630f0 drm/amdgpu: add IH_RING1_CFG headers for IH v6.0 
Add offsets, mask and shift macros for IH v6.0
which are needed to configure ring1 client irq
redirection.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-18 23:46:31 -04:00
Rodrigo Siqueira
be239684b1 drm/amd/display: Add missing registers 
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-09 22:06:16 -04:00
Rodrigo Siqueira
e7927b2914 drm/amd/display: Add some missing debug registers 
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-09 22:05:50 -04:00
Hawking Zhang
c9d7f802e6 drm/amdgpu: Add smuio v14_0_2 ip headers (v4) 
v1: Add smuio v14_0_2 register offset and shift masks
    header files. (Hawking)
v2: Update smuio v14_0_2 register offset and shift masks
    header files to RE2. (Likun)
v3: Update smuio v14_0_2 register offset and shift masks
    header files to RE2.5. (Likun)
v4: Clean up smuio v14_0_2 ip headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-20 13:38:16 -04:00
Rodrigo Siqueira
0ba7ad7e42 drm/amd/display: Add missing registers and offset 
[Why & How]
Registers and offset are missing. Add it back

Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-20 13:38:13 -04:00
Tao Zhou
b7b23877a2 drm/amdgpu: add new bit definitions for GC 9.0 PROTECTION_FAULT_STATUS 
Add UCE and FED bit definitions.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-20 13:37:36 -04:00
Hawking Zhang
b9e9b8eaaf drm/amdgpu: Add pcie v6_1_0 ip headers (v5) 
v1: Add pcie v6_1_0 register offset and shift masks
    header files. (Hawking)
v2: Update pcie v6_1_0 register offset and shift masks
    header files to RE2. (Likun)
v3: Update pcie v6_1_0 register offset and shift masks
    header files to RE2.5. (Likun)
v4: Update pcie v6_1_0 register offset and shift masks
    header files to RE3. (Likun)
v5: Updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-07 15:32:38 -05:00
Hawking Zhang
d9b772420f drm/amdgpu: Add nbif v6_3_1 ip headers (v5) 
v1: Add nbif v6_3_1 register offset and shift masks
    header files. (Hawking)
v2: Update nbif v6_3_1 register offset and shift masks
    header files to RE2. (Likun)
v3: Update nbif v6_3_1 register offset and shift masks
    header files to RE2.5. (Likun)
v4: Update nbif v6_3_1 register offset and shift masks
    header files to RE3. (Likun)
v5: Updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-07 15:32:31 -05:00
Hamza Mahfooz
3a80fe500e drm/amd: add register headers for DCN351 
Add register headers for DCN 3.5.1.

Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-04 15:59:07 -05:00
Asad Kamal
86a08f1af2 Revert "drm/amdgpu: Add pci usage to nbio v7.9" 
Remove implementation to get pcie usage for nbio v7.9
as pcie usage is handled by fw

This reverts commit 59070fd9cc.

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-02-22 10:15:26 -05:00
Yifan Zhang
dc84f52eb2 drm/amdgpu/nbio: Add NBIO 7.11.1 Support 
Fix up doorbell setup and clockgating.

v2: squash in fixes (Alex)

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-02-16 15:42:03 -05:00
Hawking Zhang
f00c8157b6 drm/amdgpu: Add mp v14_0_2 ip headers (v5) 
v1: Add mp v14_0_2 register offset and shift masks
    header files. (Hawking)
v2: Update mp v14_0_2 register offset and shift masks
    header files to RE2. (Likun)
v3: Update mp v14_0_2 register offset and shift masks
    header files to RE2.5. (Likun)
v4: Update mp v14_0_2 register offset and shift masks
    header files to RE3. (Likun)
v5: Updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-02-14 17:15:41 -05:00
Hawking Zhang
5995a22f2e drm/amdgpu: Add vcn v5_0_0 ip headers (v5) 
v1: Add vcn v5_0_0 register offset and shift masks
    header files. (Hawking)
v2: Update vcn v5_0_0 register offset and shift masks
    header files to RE2. (Likun)
v3: Update vcn v5_0_0 register offset and shift masks
    header files to RE2.5. (Likun)
v4: Update vcn v5_0_0 register offset and shift masks
    header files to RE3. (Likun)
v5: Clean up vcn v5_0_0 ip headers. (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-02-12 16:10:05 -05:00
Hawking Zhang
5fb2f479b0 drm/amdgpu: Add hdp v7_0_0 ip headers (v3) 
v1: Add hdp v7_0_0 register offset and shift masks
    header files (Hawking)
v2: Update hdp v7_0_0 register offset and shift masks
    header files for RE2.5 (Likun)
v3: Clean up hdp v7_0_0 ip headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-02-12 16:09:50 -05:00
Hawking Zhang
33c0c80ae5 drm/amdgpu: Add osssys v7_0_0 ip headers (v4) 
v1: Add osssys v7_0_0 register offset and shift masks
    header files. (Hawking)
v2: Update osssys v7_0_0 register offset and shift masks
    header files to RE2. (Likun)
v3: Update osssys v7_0_0 register offset and shift masks
    header files to RE2.5. (Likun)
v4: Clean up osssys v7_0_0 ip headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-02-12 16:09:06 -05:00
Hawking Zhang
f902bf5dd4 drm/amdgpu: Add lsdma v7_0_0 ip headers (v3) 
v1: Add lsdma v7_0_0 register offset and shift masks
    header files (Hawking)
v2: Update lsdma v7_0_0 register offset and shift masks
    header files for RE2.5 (Likun)
v3: Clean up lsdma v7_0_0 ip headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-02-12 16:08:34 -05:00
Hawking Zhang
0be41f31a9 drm/amdgpu: Add athub v4_1_0 ip headers (v5) 
v1: Add athub v4_1_0 register offset and shift masks
    header files. (Hawking)
v2: Update athub v4_1_0 register offset and shift masks
    header files to RE2. (Likun)
v3: Update athub v4_1_0 register offset and shift masks
    header files to RE2.5 (Likun)
v4: Update athub v4_1_0 register offset and shift masks
    header files to RE3. (Likun)
v5: Clean up athub v4_1_0 ip headers. (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-02-12 16:07:48 -05:00
Rodrigo Siqueira
b8e9a995fb drm/amd/include: Add missing registers/mask for DCN316 and 350 
Cc: Jun Lei <Jun.Lei@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-01-29 15:34:33 -05:00
Yifan Zhang
8f8cb7124e drm/amdgpu: update headers for nbio v7.11 
This patch is to update headers for nbio v7.11.

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-01-15 18:31:41 -05:00
Tom St Denis
44f3356e36 drm/amd/amdgpu: Add SMUIO headers for 10.0.2 
These were requested by a UMR user for debugging purposes.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-12-06 15:22:37 -05:00
Li Ma
ee95135bfe drm/amdgpu: add init_registers for nbio v7.11 
enable init_registers callback func for nbio v7.11.

Signed-off-by: Li Ma <li.ma@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-11-29 16:49:00 -05:00
Alex Sierra
20b07b0cb3 drm/amdgpu: Force order between a read and write to the same address 
Setting register to force ordering to prevent read/write or write/read
hazards for un-cached modes.

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-11-29 16:48:59 -05:00
Daniel Miess
5f70d4ff80 drm/amd/display: Enable DCN clock gating for DCN35 
[WHY & HOW]
Enable DCN clock gating for DCN35.
Disable DTBCLK gate before link training
and re-enable afterwards

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-11-17 09:30:50 -05:00
Hawking Zhang
38a64e3a33 drm/amdgpu: Add C2PMSG_109/126 reg field shift/masks 
Add MP0_C2PMSG_109/126 register field shift/masks
that are used to identify boot status by driver.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-11-03 12:18:33 -04:00
Li Ma
fa9dd7a285 drm/amdgpu: fix missing stuff in NBIO v7.11 
add get_clockgating_state, update_medium_grain_light_sleep and
update_medium_grain_clock_gating in nbio_v7_11_funcs
v1:
add missing funcs in nbio_v7_11.c
v2:
modify the if condition and add spport for nbio v7.11 clockgating.

Signed-off-by: Li Ma <li.ma@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-10-20 15:11:28 -04:00
Alex Deucher
20ace55bc0 drm/amdgpu: update to the latest GC 11.5 headers 
Add some additional bitfields.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-10-19 18:26:51 -04:00
Lang Yu
4661482b9c drm/amdgpu: correct NBIO v7.11 programing 
Use v7.7 before, switch to v7.11 now.
Fix incorrect programing.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-10-13 11:33:21 -04:00
Yang Wang
25396684b5 drm/amd/pm: add smu_13_0_6 mca dump support 
v1:
implement smu_v13_0_6 mca bank interface.

v2:
- remove unnecessary lock
- move MCMP1_* macros to mp_13_0_6_sh_mask.h file

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-20 16:24:06 -04:00
Candice Li
806c6b3d6f drm/amd: Add umc v12_0_0 ip headers 
Add umc v12_0_0 ip headers.

Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-06 14:35:12 -04:00
Lang Yu
2c98de563b drm/amdgpu: add UMSCH 4.0 register headers 
Add headers for UMSCH 4.0.

v2: updates (Alex)

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:35:06 -04:00
Saleemkhan Jamadar
c2066c5fb3 drm/amdgpu: add vcn 4_0_5 header files 
Add VCN 4.0.5 registers

v2 - Add license header (Alexander Deucher)
v3 - updates (Alex)

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:25 -04:00
Lang Yu
2edc59309f drm/amdgpu: add VPE 6.1.0 header files 
Add initial headers. (Ray)
Update to align with hardware changes. (Lang)
Updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:17 -04:00
Qingqing Zhuo
ea629e5cf2 drm/amd/display: Add dcn35 register header files 
[Why & How]
Add register headers for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:13 -04:00