d510568970
perf arm_spe: Set HITM flag
...
Since FEAT_SPEv1p4, Arm SPE provides two extra events: "Cache data
modified" and "Data snooped".
Set the snoop mode as:
- If both the "Cache data modified" event and the "Data snooped" event
are set, which indicates a load operation that snooped from a outside
cache and hit a modified copy, set the HITM flag to inspect false
sharing.
- If the snooped event bit is not set, and the snooped event has been
supported by the hardware, set as NONE mode (no snoop operation).
- If the snooped event bit is not set, and the event is not supported or
absent the events info in the meta data, set as NA mode (not
available).
Don't set any mode for only "Cache data modified" event, as it hits a
local modified copy.
Reviewed-by: James Clark <james.clark@linaro.org >
Signed-off-by: Leo Yan <leo.yan@arm.com >
Cc: Adrian Hunter <adrian.hunter@intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Ali Saidi <alisaidi@amazon.com >
Cc: German Gomez <german.gomez@arm.com >
Cc: Ian Rogers <irogers@google.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Will Deacon <will@kernel.org >
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2025-09-19 12:14:29 -03:00
786e7e7a50
perf arm_spe: Fill memory levels for FEAT_SPEv1p4
...
Starting with FEAT_SPEv1p4, Arm SPE provides information on Level 2 data
cache and recently fetched events. This patch fills in the memory levels
for these new events.
The recently fetched events are matched to line-fill buffer (LFB). In
general, the latency for accessing LFB is higher than accessing L1 cache
but lower than accessing L2 cache. Thus, it locates in the memory
hierarchy information between L1 cache and L2 cache.
Reviewed-by: James Clark <james.clark@linaro.org >
Signed-off-by: Leo Yan <leo.yan@arm.com >
Cc: Adrian Hunter <adrian.hunter@intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Ali Saidi <alisaidi@amazon.com >
Cc: German Gomez <german.gomez@arm.com >
Cc: Ian Rogers <irogers@google.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Will Deacon <will@kernel.org >
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2025-09-19 12:14:28 -03:00
45854b6d77
perf arm_spe: Directly propagate raw event
...
Two sets of event bits are defined: one for generating samples and
another are raw event bits used in the backend decoder. Reduce the
redundancy by using the raw event bits directly in the frontend code.
To avoid overflow issues, change the type of the event variable from
enum to u64.
Reviewed-by: James Clark <james.clark@linaro.org >
Signed-off-by: Leo Yan <leo.yan@arm.com >
Cc: Adrian Hunter <adrian.hunter@intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Ali Saidi <alisaidi@amazon.com >
Cc: German Gomez <german.gomez@arm.com >
Cc: Ian Rogers <irogers@google.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Will Deacon <will@kernel.org >
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2025-09-19 12:14:28 -03:00
846b62b343
perf arm-spe: Add support for SPE Data Source packet on HiSilicon HIP12
...
Add data source encoding for HiSilicon HIP12 and coresponding mapping
to the perf's memory data source. This will help to synthesize the data
and support upper layer tools like perf-mem and perf-c2c.
Reviewed-by: Leo Yan <leo.yan@arm.com >
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com >
Cc: CaiJingtao <caijingtao@huawei.com >
Cc: Catalin Marinas <catalin.marinas@arm.com >
Cc: Ian Rogers <irogers@google.com >
Cc: Ingo Molnar <mingo@redhat.com >
Cc: James Clark <james.clark@linaro.org >
Cc: Jiri Olsa <jolsa@kernel.org >
Cc: John Garry <john.g.garry@oracle.com >
Cc: Jonathan Cameron <jonathan.cameron@huawei.com >
Cc: Junhao He <hejunhao3@huawei.com >
Cc: Leo Yan <leo.yan@linux.dev >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Will Deacon <will@kernel.org >
Cc: Yushan Wang <wangyushan12@huawei.com >
Cc: Zeng Tao <prime.zeng@hisilicon.com >
Cc: xueshan2@huawei.com
Link: https://lore.kernel.org/r/20250425033845.57671-3-yangyicong@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2025-05-27 17:57:58 -03:00
2cc2f258a9
perf arm-spe: Support previous branch target (PBT) address
...
When FEAT_SPE_PBT is implemented, the previous branch target address
(named as PBT) before the sampled operation, will be recorded.
This commit first introduces a 'prev_br_tgt' field in the record for
saving the PBT address in the decoder.
If the current operation is a branch instruction, by combining with PBT,
it can create a chain with two consecutive branches. As the branch
stack stores branches in descending order, meaning a newer branch is
stored in a lower entry in the stack. Arm SPE stores the latest branch
in the first entry of branch stack, and the previous branch coming from
PBT is stored into the second entry.
Otherwise, if current operation is not a branch, the last branch will be
saved for PBT only. PBT lacks associated information such as branch
source address, branch type, and events. The branch entry fills zeros
for the corresponding fields and only set its target address.
After:
perf script -f --itrace=bl -F flags,addr,brstack
jcc ffff800080187914 0xffff8000801878fc/0xffff800080187914/P/-/-/1/COND/- 0x0/0xffff8000801878f8/-/-/-/0//-
jcc ffff8000802d12d8 0xffff8000802d12f8/0xffff8000802d12d8/P/-/-/1/COND/- 0x0/0xffff8000802d12ec/-/-/-/0//-
jcc ffff8000813fe200 0xffff8000813fe20c/0xffff8000813fe200/P/-/-/1/COND/- 0x0/0xffff8000813fe200/-/-/-/0//-
jcc ffff8000813fe200 0xffff8000813fe20c/0xffff8000813fe200/P/-/-/1/COND/- 0x0/0xffff8000813fe200/-/-/-/0//-
jmp ffff800081410980 0xffff800081419108/0xffff800081410980/P/-/-/1//- 0x0/0xffff800081419104/-/-/-/0//-
return ffff80008036e064 0xffff80008141ba84/0xffff80008036e064/P/-/-/1/RET/- 0x0/0xffff80008141ba60/-/-/-/0//-
jcc ffff8000803d54f0 0xffff8000803d54e8/0xffff8000803d54f0/P/-/-/1/COND/- 0x0/0xffff8000803d54e0/-/-/-/0//-
jmp ffff80008015e468 0xffff8000803d46dc/0xffff80008015e468/P/-/-/1//- 0x0/0xffff8000803d46c8/-/-/-/0//-
jmp ffff8000806e2d50 0xffff80008040f710/0xffff8000806e2d50/P/-/-/1//- 0x0/0xffff80008040f6e8/-/-/-/0//-
jcc ffff800080721704 0xffff8000807216b4/0xffff800080721704/P/-/-/1/COND/- 0x0/0xffff8000807216ac/-/-/-/0//-
Reviewed-by: Ian Rogers <irogers@google.com >
Reviewed-by: James Clark <james.clark@linaro.org >
Signed-off-by: Leo Yan <leo.yan@arm.com >
Link: https://lore.kernel.org/r/20250304111240.3378214-13-leo.yan@arm.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org >
2025-03-05 09:13:20 -08:00
5c1b158396
perf arm-spe: Fill branch operations and events to record
...
The new added branch operations and events are filled into record, the
information will be consumed when synthesizing samples.
Reviewed-by: Ian Rogers <irogers@google.com >
Reviewed-by: James Clark <james.clark@linaro.org >
Signed-off-by: Leo Yan <leo.yan@arm.com >
Link: https://lore.kernel.org/r/20250304111240.3378214-10-leo.yan@arm.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org >
2025-03-05 09:13:20 -08:00
9e7a00ec6a
perf arm-spe: Add support for SPE Data Source packet on AmpereOne
...
Decode SPE Data Source packets on AmpereOne. The field is IMPDEF.
Reviewed-by: Leo Yan <leo.yan@arm.com >
Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com >
Cc: Adrian Hunter <adrian.hunter@intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Graham Woodward <graham.woodward@arm.com >
Cc: Ian Rogers <irogers@google.com >
Cc: Ingo Molnar <mingo@redhat.com >
Cc: James Clark <james.clark@linaro.org >
Cc: Jiri Olsa <jolsa@kernel.org >
Cc: John Garry <john.g.garry@oracle.com >
Cc: Kan Liang <kan.liang@linux.intel.com >
Cc: Leo Yan <leo.yan@linux.dev >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Mike Leach <mike.leach@linaro.org >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Will Deacon <will@kernel.org >
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20241108202946.16835-3-ilkka@os.amperecomputing.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2024-12-09 17:52:41 -03:00
50b8f1d5bf
perf arm-spe: Rename the common data source encoding
...
The Neoverse CPUs follow the common data source encoding, and other
CPU variants can share the same format.
Rename the CPU list and data source definitions as common data source
names. This change prepares for appending more CPU variants.
Signed-off-by: Leo Yan <leo.yan@arm.com >
Reviewed-by: James Clark <james.clark@linaro.org >
Link: https://lore.kernel.org/r/20241003185322.192357-3-leo.yan@arm.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org >
2024-10-14 12:04:31 -07:00
0066015a3d
perf arm-spe: Refactor arm-spe to support operation packet type
...
Extend the decoder of Arm SPE records to support more fields from the
operation packet type.
Not all fields are being decoded by this commit. Only those needed to
support the use-case SVE load/store/other operations.
Suggested-by: Leo Yan <leo.yan@linaro.org >
Signed-off-by: German Gomez <german.gomez@arm.com >
Acked-by: Ian Rogers <irogers@google.com >
Cc: Adrian Hunter <adrian.hunter@intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Anshuman.Khandual@arm.com
Cc: Ingo Molnar <mingo@redhat.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Cc: John Garry <john.g.garry@oracle.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Mike Leach <mike.leach@linaro.org >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Will Deacon <will@kernel.org >
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20230320151509.1137462-2-james.clark@arm.com
Signed-off-by: James Clark <james.clark@arm.com >
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2023-03-20 19:27:52 -03:00
4e6430cbb1
perf arm-spe: Use SPE data source for neoverse cores
...
When synthesizing data from SPE, augment the type with source information
for Arm Neoverse cores. The field is IMPLDEF but the Neoverse cores all use
the same encoding. I can't find encoding information for any other SPE
implementations to unify their choices with Arm's thus that is left for
future work.
This change populates the mem_lvl_num for Neoverse cores as well as the
deprecated mem_lvl namespace.
Reviewed-by: German Gomez <german.gomez@arm.com >
Reviewed-by: Leo Yan <leo.yan@linaro.org >
Signed-off-by: Ali Saidi <alisaidi@amazon.com >
Tested-by: Leo Yan <leo.yan@linaro.org >
Cc: Adrian Hunter <adrian.hunter@intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Anshuman Khandual <anshuman.khandual@arm.com >
Cc: Gustavo A. R. Silva <gustavoars@kernel.org >
Cc: Ian Rogers <irogers@google.com >
Cc: Ingo Molnar <mingo@redhat.com >
Cc: James Clark <james.clark@arm.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Cc: John Garry <john.garry@huawei.com >
Cc: Kajol Jain <kjain@linux.ibm.com >
Cc: Like Xu <likexu@tencent.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Mike Leach <mike.leach@linaro.org >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Timothy Hayes <timothy.hayes@arm.com >
Cc: Will Deacon <will@kernel.org >
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20220811062451.435810-4-leo.yan@linaro.org
Signed-off-by: Leo Yan <leo.yan@linaro.org >
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2022-08-11 19:12:01 -03:00
b0fde9c6e2
perf arm-spe: Add SPE total latency as PERF_SAMPLE_WEIGHT
...
Use total latency info in the SPE counter packet as sample weight so
that we can see it in local_weight and (global) weight sort keys.
Maybe we can use PERF_SAMPLE_WEIGHT_STRUCT to support ins_lat as well
but I'm not sure which latency it matches. So just adding total latency
first.
Reviewed-by: Leo Yan <leo.yan@linaro.org >
Signed-off-by: Namhyung Kim <namhyung@kernel.org >
Cc: Andi Kleen <ak@linux.intel.com >
Cc: German Gomez <german.gomez@arm.com >
Cc: Ian Rogers <irogers@google.com >
Cc: James Clark <james.clark@arm.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Stephane Eranian <eranian@google.com >
Link: http://lore.kernel.org/lkml/20211201220855.1260688-1-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2021-12-16 12:18:11 -03:00
169de64f5d
perf arm-spe: Save context ID in record
...
This patch is to save context ID in record, this will be used to set TID
for samples.
Reviewed-by: Leo Yan <leo.yan@linaro.org >
Signed-off-by: German Gomez <german.gomez@arm.com >
Acked-by: Namhyung Kim <namhyung@kernel.org >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: John Garry <john.garry@huawei.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Mathieu Poirier <mathieu.poirier@linaro.org >
Cc: Will Deacon <will@kernel.org >
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20211111133625.193568-4-german.gomez@arm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2021-11-13 18:11:51 -03:00
97ae666ae0
perf arm-spe: Store operation type in packet
...
This patch is to store operation type in packet structure.
Signed-off-by: Leo Yan <leo.yan@linaro.org >
Reviewed-by: James Clark <james.clark@arm.com >
Tested-by: James Clark <james.clark@arm.com >
Cc: Adrian Hunter <adrian.hunter@intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Al Grant <al.grant@arm.com >
Cc: Andre Przywara <andre.przywara@arm.com >
Cc: Ingo Molnar <mingo@redhat.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: John Garry <john.garry@huawei.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Mathieu Poirier <mathieu.poirier@linaro.org >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Wei Li <liwei391@huawei.com >
Cc: Will Deacon <will@kernel.org >
Signed-off-by: James Clark <james.clark@arm.com >
Link: https://lore.kernel.org/r/20210211133856.2137-3-james.clark@arm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2021-02-12 17:43:24 -03:00
265cfb9586
perf arm-spe: Store memory address in packet
...
This patch is to store virtual and physical memory addresses in packet,
which will be used for memory samples.
Signed-off-by: Leo Yan <leo.yan@linaro.org >
Reviewed-by: James Clark <james.clark@arm.com >
Tested-by: James Clark <james.clark@arm.com >
Cc: Adrian Hunter <adrian.hunter@intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Al Grant <al.grant@arm.com >
Cc: Andre Przywara <andre.przywara@arm.com >
Cc: Ingo Molnar <mingo@redhat.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: John Garry <john.garry@huawei.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Mathieu Poirier <mathieu.poirier@linaro.org >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Wei Li <liwei391@huawei.com >
Cc: Will Deacon <will@kernel.org >
Link: https://lore.kernel.org/r/20210211133856.2137-2-james.clark@arm.com
Signed-off-by: James Clark <james.clark@arm.com >
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2021-02-12 17:43:21 -03:00
889d1a675f
perf arm-spe: Refactor event type handling
...
Move the enums of event types to arm-spe-pkt-decoder.h, thus function
arm_spe_pkt_desc_event() can use them for bitmasks.
Suggested-by: Andre Przywara <andre.przywara@arm.com >
Signed-off-by: Leo Yan <leo.yan@linaro.org >
Reviewed-by: Andre Przywara <andre.przywara@arm.com >
Acked-by: Will Deacon <will@kernel.org >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Al Grant <Al.Grant@arm.com >
Cc: Arnaldo Carvalho de Melo <acme@kernel.org >
Cc: Dave Martin <Dave.Martin@arm.com >
Cc: Ingo Molnar <mingo@redhat.com >
Cc: James Clark <james.clark@arm.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: John Garry <john.garry@huawei.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Mathieu Poirier <mathieu.poirier@linaro.org >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Wei Li <liwei391@huawei.com >
Link: https://lore.kernel.org/r/20201119152441.6972-11-leo.yan@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2020-11-26 09:31:46 -03:00
a54ca19498
perf arm-spe: Support synthetic events
...
After the commit ffd3d18c20tanxiaojun@huawei.com >
Tested-by: James Clark <james.clark@arm.com >
Cc: Adrian Hunter <adrian.hunter@intel.com >
Cc: Al Grant <al.grant@arm.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Andi Kleen <ak@linux.intel.com >
Cc: Ian Rogers <irogers@google.com >
Cc: Jin Yao <yao.jin@linux.intel.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: Leo Yan <leo.yan@linaro.org >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Mathieu Poirier <mathieu.poirier@linaro.org >
Cc: Mike Leach <mike.leach@linaro.org >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Will Deacon <will@kernel.org >
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lore.kernel.org/lkml/20200530122442.490-4-leo.yan@linaro.org
Signed-off-by: James Clark <james.clark@arm.com >
Signed-off-by: Leo Yan <leo.yan@linaro.org >
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2020-06-01 12:24:23 -03:00
Leo Yan
Yicong Yang
Ilkka Koskinen
German Gomez
Ali Saidi
Namhyung Kim
Leo Yan
Tan Xiaojun