Pull SoC driver updates from Arnd Bergmann:
"Lots of platform specific updates for Qualcomm SoCs, including a new
TEE subsystem driver for the Qualcomm QTEE firmware interface.
Added support for the Apple A11 SoC in drivers that are shared with
the M1/M2 series, among more updates for those.
Smaller platform specific driver updates for Renesas, ASpeed,
Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale
SoCs.
Driver updates in the cache controller, memory controller and reset
controller subsystems.
SCMI firmware updates to add more features and improve robustness.
This includes support for having multiple SCMI providers in a single
system.
TEE subsystem support for protected DMA-bufs, allowing hardware to
access memory areas that managed by the kernel but remain inaccessible
from the CPU in EL1/EL0"
* tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits)
soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
soc: fsl: qe: Change GPIO driver to a proper platform driver
tee: fix register_shm_helper()
pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
dt-bindings: spmi: Add Apple A11 and T2 compatible
serial: qcom-geni: Load UART qup Firmware from linux side
spi: geni-qcom: Load spi qup Firmware from linux side
i2c: qcom-geni: Load i2c qup Firmware from linux side
soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
soc: qcom: geni-se: Cleanup register defines and update copyright
dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
Documentation: tee: Add Qualcomm TEE driver
tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
tee: qcom: add primordial object
tee: add Qualcomm TEE driver
tee: increase TEE_MAX_ARG_SIZE to 4096
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
tee: add close_context to TEE driver operation
...
Pull spi updates from Mark Brown:
"There's one big core change in this release, Jonas Gorski has
addressed the issues with multiple chip selects which makes things
more robust and stable. Otherwise there's quite a bit of driver work,
as well as some new drivers several existing drivers have had quite a
bit of work done on them.
Possibly the most interesting thing is the VirtIO driver, this is
apparently useful for some automotive applications which want to keep
as small and robust a host system as they can, moving less critical
functionality into guests.
- James Clark has done some substantial updates on the Freescale DSPI
driver, porting in code from the BSP and building onm top of that
to fix some bugs and increase performance
- Jonas Gorski has fixed the issues with handling multple chip
selects, making things more robust and scalable
- Support for higher performance modes in the NXP FSPI driver from
Haibo Chen
- Removal of the obsolete S3C2443 driver, the underlying SoC support
has been removed from the kernel
- Support for Amlogic AL113L2, Atmel SAMA7D65 and SAM9x7 and for
VirtIO controllers"
* tag 'spi-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (74 commits)
spi: ljca: Remove Wentong's e-mail address
spi: rename SPI_CS_CNT_MAX => SPI_DEVICE_CS_CNT_MAX
spi: reduce device chip select limit again
spi: don't check spi_controller::num_chipselect when parsing a dt device
spi: drop check for validity of device chip selects
spi: move unused device CS initialization to __spi_add_device()
spi: keep track of number of chipselects in spi_device
spi: fix return code when spi device has too many chipselects
SPI: Add virtio SPI driver
virtio-spi: Add virtio-spi.h
virtio: Add ID for virtio SPI
spi: rpc-if: Add resume support for RZ/G3E
spi: rpc-if: Drop deprecated SIMPLE_DEV_PM_OPS
spi: spi-qpic-snand: simplify clock handling by using devm_clk_get_enabled()
spi: spi-nxp-fspi: Add OCT-DTR mode support
spi: spi-nxp-fspi: add the support for sample data from DQS pad
spi: spi-nxp-fspi: Add the DDR LUT command support
spi: spi-nxp-fspi: set back to dll override mode when clock rate < 100MHz
spi: spi-nxp-fspi: extract function nxp_fspi_dll_override()
spi: atmel-quadspi: Add support for sama7d65 QSPI
...
Apple SoC driver updates for 6.18
Krzysztof Kozlowski asked us to move away from generic compatibles:
- Adjust all dt-bindings to use apple,t8103-XXXX instead of apple,XXXX
as fallback and add a comment that the old generic list should no
longer be extended.
- Add new fallback compatibles to pinctrl, pmdomain, spi, and mca
drivers. These changes have been Acked by their subsystem maintainers
to be merged through our tree together with the dt-bindings.
Support for pre-M1 Apple Silicon:
- SART and mailbox gain support for Apple's A11, which are both
required for NVMe.
- NVMe also gains support for Apple's A11 and the nvme maintainers
prefer that we merge this through the soc tree together with
the mailbox and SART changes.
- SPMI compatibles for A11 and T2 have been added, also going through
the soc tree due to conflicts with the generic compatible removal and
because no driver change is required.
Signed-off-by: Sven Peter <sven@kernel.org>
* tag 'apple-soc-drivers-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux: (32 commits)
pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
dt-bindings: spmi: Add Apple A11 and T2 compatible
spi: apple: Add "apple,t8103-spi" compatible
ASoC: apple: mca: Add "apple,t8103-mca" compatible
pinctrl: apple: Add "apple,t8103-pinctrl" as compatible
spi: dt-bindings: apple,spi: Add t6020-spi compatible
ASoC: dt-bindings: apple,mca: Add t6020-mca compatible
dt-bindings: dma: apple,admac: Add t6020-admac compatible
dt-bindings: clock: apple,nco: Add t6020-nco compatible
dt-bindings: watchdog: apple,wdt: Add t6020-wdt compatible
dt-bindings: spmi: apple,spmi: Add t6020-spmi compatible
dt-bindings: mfd: apple,smc: Add t6020-smc compatible
dt-bindings: net: bcm4329-fmac: Add BCM4388 PCI compatible
dt-bindings: net: bcm4377-bluetooth: Add BCM4388 compatible
dt-bindings: nvme: apple: Add apple,t6020-nvme-ans2 compatible
dt-bindings: iommu: apple,sart: Add apple,t6020-sart compatible
dt-bindings: gpu: apple,agx: Add agx-{g14s,g14c,g14d} compatibles
dt-bindings: mailbox: apple,mailbox: Add t6020 compatible
dt-bindings: pinctrl: apple,pinctrl: Add apple,t6020-pinctrl compatible
dt-bindings: iommu: dart: Add apple,t6020-dart compatible
...
Link: https://lore.kernel.org/r/20250920123028.49973-1-sven@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
More Qualcomm device driver updates for v6.18
Introduce support for loading firmware into the QUP serial engines from
Linux, which allows deferring selection of which protocol (uart, i2c,
spi, etc) a given SE should have until the OS loads.
Also introduce the "object invoke" interface in the SCM driver, to
provide interface to the Qualcomm TEE driver.
* tag 'qcom-drivers-for-6.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
serial: qcom-geni: Load UART qup Firmware from linux side
spi: geni-qcom: Load spi qup Firmware from linux side
i2c: qcom-geni: Load i2c qup Firmware from linux side
soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
soc: qcom: geni-se: Cleanup register defines and update copyright
dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
firmware: qcom: scm: add support for object invocation
firmware: qcom: tzmem: export shm_bridge create/delete
Link: https://lore.kernel.org/r/20250921020225.595403-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Merge series from Biju Das <biju.das.jz@bp.renesas.com>:
On RZ/G3E using PSCI, s2ram powers down the SoC. After resume,
reinitialize the hardware for SPI operations.
Also Replace the macro SIMPLE_DEV_PM_OPS->DEFINE_SIMPLE_DEV_PM_OPS macro
and use pm_sleep_ptr(). This lets us drop the check for CONFIG_PM_SLEEP
and __maybe_unused attribute from PM functions.
Merge series from Haixu Cui <quic_haixcui@quicinc.com>:
This is the 10th version of the virtio SPI Linux driver patch series which is
intended to be compliant with the upcoming virtio specification
version 1.4. The specification can be found in repository:
https://github.com/oasis-tcs/virtio-spec.git branch virtio-1.4.
Merge series from Jonas Gorski <jonas.gorski@gmail.com>:
This series aims at cleaning up the current multi CS parts and removing
the CS limit per controller that was introduced with the multi CS
support.
To do this, store the assigned chip selects per device in
spi_device::num_chipselects, which allows us to use that instead of
SPI_CS_CNT_MAX for most loops, as well as remove the check for
SPI_INVALID_CS for any chip select.
This should hopefully make it obvious that SPI_CS_CNT_MAX only limits
accesses to arrays indexed by the number of chip selects of a device,
not the controller, and we can remove the check for
spi_controller::num_chipselects being less than SPI_CS_CNT_MAX in device
registration (which was the wrong place to do that anyway).
After having done that, we can reduce SPI_CS_CNT_MAX again to 4 without
breaking devices on higher CS lines.
Finally, rename SPI_CS_CNT_MAX to SPI_DEVICE_CNT_MAX to make it more
clear that this limit only applies to devices, not controllers.
There are still more issues left, but these can be addressed in future
submissions:
* The code allows multi-cs devices for any controller, as long as the
device does not set parallel-memories.
* No current spi controller driver handles logical chip selects other
than the first one, and always use it, regardless what cs_index_mask
says.
* While most spi controllers should be able to handle devices that have
multiple cs that just get enabled selectively, but not at the same
time, there is no way to tell that to the core (ties into the above).
* There is no parallel memories/multi cs flag for devices, so any
implementing driver needs to check the device tree node, making it
impossible to register these kind of devices via platform code.
Do not validate spi_controller::num_chipselect against SPI_CS_CNT_MAX
when parsing an spi device firmware node.
Firstly this is the wrong place, and this should be done while
registering/validating the controller. Secondly, there is no reason for
that check, as SPI_CS_CNT_MAX controls the amount of chipselects a
device may have, not a controller may have.
So drop that check as it needlessly limits controllers to SPI_CS_CNT_MAX
number of chipselects.
Likewise, drop the check for number of device chipselects larger than
controller's number of chipselects, as __spi_add_device() will already
catch that as either one of the chip selects will be out of range, or
there is a duplicate one.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-6-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
There are several places where we need to iterate over a device's
chipselect. To be able to do it efficiently, store the number of
chipselects in spi_device, like we do for controllers.
Since we now use a device supplied value, add a check to make sure it
isn't more than we can support.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-3-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
If the cached contents of the CHCONF register doesn't have the FORCE bit
set, the setup() function failed to set the relevant idle state of the
SPI_CLK pin. In such case, the SPI_CLK's idle state is reached later with
set_cs(), but it's too late for the first SPI transfer which fails since
the CS is asserted before the clock reaching its idle state.
Add a first write in setup() that always sets the FORCE bit.
Keep the current write afterwards to ensure the FORCE bit won't stay in
the cached contents of the CHCONF register unless it's intended.
Signed-off-by: Bastien Curutchet (Schneider Electric) <bastien.curutchet@bootlin.com>
Link: https://patch.msgid.link/20250912-omap-spi-fix-v1-1-f925b0d27ede@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Replace SIMPLE_DEV_PM_OPS->DEFINE_SIMPLE_DEV_PM_OPS macro and use
pm_sleep_ptr(). This lets us drop the check for CONFIG_PM_SLEEP, and
reduces kernel size in case CONFIG_PM or CONFIG_PM_SLEEP is disabled,
while increasing build coverage.
Also drop the __maybe_unused attribute from PM functions.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20250921112649.104516-2-biju.das.jz@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Merge series from Dharma Balasubiramani <dharma.b@microchip.com>:
This patch series adds support for SAM9X7 and sama7d65 QSPI controller
along with the SoC-specific capabilities.
Merge series from Haibo Chen <haibo.chen@nxp.com>:
this patch set add DTR mode support for flexspi.
For DTR mode, flexspi only support 8D-8D-8D mode.
Patch 1~2 extract nxp_fspi_dll_override(), prepare for adding the DTR mode.
in nor suspend, it will disable DTR mode, and enable DTR mode back
in nor resume. this require the flexspi driver has the ability to
set back to dll override mode in STR mode when clock rate < 100MHz.
Patch 3 Add the DDR LUT command support. flexspi use LUT command to handle
the dtr/str mode.
Patch 4 add the logic of sample clock source selection for STR/DTR mode
STR use the default mode 0, sample based on the internal dummy pad.
DTR use the mode 3, sample based on the external DQS pad, so this
board and device connect the DQS pad.
adjust the clock rate for DTR mode, when detect the DDR LUT command,
flexspi will automatically div 2 of the root clock and output to device.
Patch 5 finally add the DTR support in default after the upper 4 patches's
prepareation. Since lx2160a do not implement DQS pad, so can't support
this DTR mode.
The devm_clk_get_enabled() function prepares and enables the
particular clock, which then automatically gets disabled and
unprepared on probe failure and on device removal.
Use that function instead of devm_clk_get() and remove the
clk_prepare_enable()/clk_disable_unprepare() calls in order
to simplify the code.
This also ensures that the clocks are handled in the correct
order during device removal.
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://patch.msgid.link/20250916-qpic-snand-devm_clk_get_enabled-v1-1-09953493b7f1@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
flexspi define four mode for sample clock source selection.
Here is the list of modes:
mode 0: Dummy Read strobe generated by FlexSPI Controller and loopback
internally
mode 1: Dummy Read strobe generated by FlexSPI Controller and loopback
from DQS pad
mode 2: Reserved
mode 3: Flash provided Read strobe and input from DQS pad
In default, flexspi use mode 0 after reset. And for DTR mode, flexspi
only support 8D-8D-8D mode. For 8D-8D-8D mode, IC suggest to use mode 3,
otherwise read always get incorrect data.
For DTR mode, flexspi will automatically div 2 of the root clock
and output to device. the formula is:
device_clock = root_clock / (is_dtr ? 2 : 1)
So correct the clock rate setting for DTR mode to get the max
performance.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20250917-flexspi-ddr-v2-4-bb9fe2a01889@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Introduce capability flags for SoC-specific variations of the QuadSPI
controller:
- has_padcalib: controller supports pad calibration
- has_2xgclk: requires GCLK at half the data rate (2x clocking)
- has_dllon: controller supports DLL clock
Set `has_padcalib` for Octal controllers that provide pad calibration
support. Use `has_2xgclk` for controllers that require the GCLK to run
at twice the data rate. Differentiate SoC integration variants with the
`has_dllon` flag and set it as needed.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Link: https://patch.msgid.link/20250908-microchip-qspi-v2-3-8f3d69fdd5c9@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Mediatek SPI hardware natively supports dual and quad modes, and these
modes are already enabled for SPI flash devices under spi-mem framework
in MTK SPI controller spi-mt65xx. However, other SPI devices, such as
touch panels, are limited to single mode because spi-mt65xx lacks SPI
mode argument parsing from SPI framework for these SPI devices outside
spi-mem framework.
This patch adds dual and quad mode support for these SPI devices by
introducing a new API, mtk_spi_set_nbits, for SPI mode argument parsing.
Signed-off-by: Tim Kuo <Tim.Kuo@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20250917055839.500615-1-Tim.Kuo@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Microchip ARM64 SoC updates for v6.18:
This update includes:
- basic infrastructure support for Microchip LAN969x SoC
- SoC ARCH symbols (existing SparX-5, new LAN969x) under the
ARCH_MICROCHIP hidden symbol (already in use by AT91 in 6.17)
- addition of that new symbol for drivers that are shared by
Microchip SoC-s now and in the future
* tag 'microchip-soc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
crypto: atmel-aes: make it selectable for ARCH_MICROCHIP
char: hw_random: atmel: make it selectable for ARCH_MICROCHIP
i2c: at91: make it selectable for ARCH_MICROCHIP
spi: atmel: make it selectable for ARCH_MICROCHIP
tty: serial: atmel: make it selectable for ARCH_MICROCHIP
mfd: at91-usart: Make it selectable for ARCH_MICROCHIP
arm64: lan969x: Add support for Microchip LAN969x SoC
arm64: Add config for Microchip SoC platforms
Link: https://lore.kernel.org/r/20250915123548.13722-1-nicolas.ferre@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Currently a call to regmap_write is not being error checked because the
return checke is being performed on the variable ret and this variable
is not assigned the return value from the regmap_write call. Fix this
by adding in the missing assignment.
Fixes: 4670db6f32 ("spi: amlogic: add driver for Amlogic SPI Flash Controller")
Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Link: https://patch.msgid.link/20250913201612.1338217-1-colin.i.king@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Merge series from David Lechner <dlechner@baylibre.com>:
We have a pending major version bump for the axi-spi-engine so to
prepare for that, improve the existing version checks for feature
enablement.
Merge series from Xianwei Zhao <xianwei.zhao@amlogic.com>:
This Flash Controller is derived by adding an SPI path to the original
raw NAND controller. This controller supports two modes: raw mode and
SPI mode. The raw mode has already been implemented in the community
(drivers/mtd/nand/raw/meson_nand.c).
This submission supports the SPI mode.
Add the drivers and bindings corresponding to the SPI Flash Controller.
The 'max_cs' stores the largest chip select number. It should only
be updated when the current 'cs' is greater than existing 'max_cs'. So,
fix the condition accordingly.
Also, return failure if there are no flash device declared.
Fixes: 0f3841a5e1 ("spi: cadence-qspi: report correct number of chip-select")
CC: stable@vger.kernel.org
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Reviewed-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Message-ID: <20250905185958.3575037-4-s-k6@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
cqspi_read_setup() and cqspi_write_setup() program the address width as
the last step in the setup. This is likely to be immediately followed by
a DAC region read/write. On TI K3 SoCs the DAC region is on a different
endpoint from the register region. This means that the order of the two
operations is not guaranteed, and they might be reordered at the
interconnect level. It is possible that the DAC read/write goes through
before the address width update goes through. In this situation if the
previous command used a different address width the OSPI command is sent
with the wrong number of address bytes, resulting in an invalid command
and undefined behavior.
Read back the size register to make sure the write gets flushed before
accessing the DAC region.
Fixes: 1406234105 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
CC: stable@vger.kernel.org
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Signed-off-by: Pratyush Yadav <pratyush@kernel.org>
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Message-ID: <20250905185958.3575037-3-s-k6@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
cqspi_indirect_read_execute() and cqspi_indirect_write_execute() first
set the enable bit on APB region and then start reading/writing to the
AHB region. On TI K3 SoCs these regions lie on different endpoints. This
means that the order of the two operations is not guaranteed, and they
might be reordered at the interconnect level.
It is possible for the AHB write to be executed before the APB write to
enable the indirect controller, causing the transaction to be invalid
and the write erroring out. Read back the APB region write before
accessing the AHB region to make sure the write got flushed and the race
condition is eliminated.
Fixes: 1406234105 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
CC: stable@vger.kernel.org
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Signed-off-by: Pratyush Yadav <pratyush@kernel.org>
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Message-ID: <20250905185958.3575037-2-s-k6@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Merge series from James Clark <james.clark@linaro.org>:
Improve usability of target mode by reporting FIFO errors and increasing
the buffer size when DMA is used. While we're touching DMA stuff also
switch to non-coherent memory, although this is unrelated to target
mode.
With the combination of the commit to increase the DMA buffer size and
the commit to use non-coherent memory, the host mode performance figures
are as follows on S32G3:
# spidev_test --device /dev/spidev1.0 --bpw 8 --size <test_size> --cpha --iter 10000000 --speed 10000000
Coherent (4096 byte transfers): 6534 kbps
Non-coherent: 7347 kbps
Coherent (16 byte transfers): 447 kbps
Non-coherent: 448 kbps
Just for comparison running the same test in XSPI mode:
4096 byte transfers: 2143 kbps
16 byte transfers: 637 kbps
These tests required hacking S32G3 to use DMA in host mode, although
the figures should be representative of target mode too where DMA is
used. And the other devices that use DMA in host mode should see similar
improvements.
The on-host hardware ECC engine remains registered both when
the spi_register_controller() function returns with an error
and also on device removal.
Change the qcom_spi_probe() function to unregister the engine
on the error path, and add the missing unregistering call to
qcom_spi_remove() to avoid possible use-after-free issues.
Fixes: 7304d19090 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Message-ID: <20250903-qpic-snand-unregister-ecceng-v1-1-ef5387b0abdc@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
In target mode, the host sending more data than can be consumed would be
a common problem for any message exceeding the FIFO or DMA buffer size.
Cancel the whole message as soon as this condition is hit as the message
will be corrupted.
Only do this for target mode in a DMA transfer, it's not likely these
flags will be set in host mode so it's not worth adding extra checks. In
IRQ and polling modes we use the same transfer functions for hosts and
targets so the error flags always get checked. This is slightly
inconsistent but it's not worth doing the check conditionally because it
may catch some host programming errors in the future.
Signed-off-by: James Clark <james.clark@linaro.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Message-ID: <20250902-james-nxp-spi-dma-v6-7-f7aa2c5e56e2@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
When the device is configured as a target, the host won't stop sending
data while we're draining the buffer which leads to FIFO underflows
and corruption.
Increase the DMA buffer size to the maximum words that edma can
transfer once to reduce the chance of this happening.
In host mode, the driver is able to split up a transfer into smaller
chunks so we don't need to increase the size. While in target mode, the
length of the transfer is determined by the remote host and can be
larger than whatever default buffer size we pick. Keeping the buffer
small in host mode avoids wasting memory, but allocating the largest
possible in target mode gives the lowest possible chance of dropping any
data from the host.
While we could allocate per-transfer using the exact size of the
transfer, 128K is quite a large allocation and there is a chance it
could fail due to memory fragmentation unless it's allocated once at
init time.
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: James Clark <james.clark@linaro.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Message-ID: <20250902-james-nxp-spi-dma-v6-6-f7aa2c5e56e2@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Linus Torvalds
Arnd Bergmann
Mark Brown
Sakari Ailus
Jonas Gorski
Haixu Cui
Bastien Curutchet (Schneider Electric)
Biju Das
Gabor Juhos
Haibo Chen
Varshini Rajendran
Khairul Anuar Romli
Viken Dadhaniya
Tim Kuo
Colin Ian King
Janne Grunau
David Lechner
Feng Chen
Vignesh Raghavendra
Santhosh Kumar K
Pratyush Yadav
Robert Marko
Krzysztof Kozlowski
James Clark