Conor Dooley 5f3575cc73 dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux ...

On PolarFire SoC there are more GPIO interrupts than there are interrupt
lines available on the PLIC, and a runtime configurable mux is used to
decide which interrupts are assigned direct connections to the PLIC &
which are relegated to sharing a line.

Reviewed-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

2026-03-31 14:13:14 +01:00

..

atmel,at91rm9200-tcb.yaml

dt-bindings: Remove extra blank lines

2025-11-17 11:24:50 -06:00

microchip,mpfs-irqmux.yaml

dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux

2026-03-31 14:13:14 +01:00

microchip,mpfs-mss-top-sysreg.yaml

dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux

2026-03-31 14:13:14 +01:00

microchip,mpfs-sys-controller.yaml

dt-bindings: soc: microchip: mpfs-sys-controller: Add pic64gx compatibility

2026-03-03 17:08:41 +00:00

microchip,sparx5-cpu-syscon.yaml

…