mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-05-05 09:57:21 +02:00
Amit Sunil Dhamne
3c7df5079c
Fix comment style for enums so they're kernel-doc compliant. Signed-off-by: Amit Sunil Dhamne <amitsd@google.com> Link: https://patch.msgid.link/20260401-fix-mfd-max77759-usb-next-v1-1-174ec23ad824@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
274 lines
12 KiB
C
274 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2020 Google Inc.
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* Copyright 2025 Linaro Ltd.
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*
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* Maxim MAX77759 core driver
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*/
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#ifndef __LINUX_MFD_MAX77759_H
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#define __LINUX_MFD_MAX77759_H
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#include <linux/completion.h>
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#include <linux/mutex.h>
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#include <linux/regmap.h>
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#define MAX77759_PMIC_REG_PMIC_ID 0x00
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#define MAX77759_PMIC_REG_PMIC_REVISION 0x01
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#define MAX77759_PMIC_REG_OTP_REVISION 0x02
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#define MAX77759_PMIC_REG_INTSRC 0x22
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#define MAX77759_PMIC_REG_INTSRCMASK 0x23
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#define MAX77759_PMIC_REG_INTSRC_MAXQ BIT(3)
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#define MAX77759_PMIC_REG_INTSRC_TOPSYS BIT(1)
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#define MAX77759_PMIC_REG_INTSRC_CHGR BIT(0)
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#define MAX77759_PMIC_REG_TOPSYS_INT 0x24
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#define MAX77759_PMIC_REG_TOPSYS_INT_MASK 0x26
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#define MAX77759_PMIC_REG_TOPSYS_INT_TSHDN BIT(6)
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#define MAX77759_PMIC_REG_TOPSYS_INT_SYSOVLO BIT(5)
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#define MAX77759_PMIC_REG_TOPSYS_INT_SYSUVLO BIT(4)
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#define MAX77759_PMIC_REG_TOPSYS_INT_FSHIP BIT(0)
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#define MAX77759_PMIC_REG_I2C_CNFG 0x40
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#define MAX77759_PMIC_REG_SWRESET 0x50
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#define MAX77759_PMIC_REG_CONTROL_FG 0x51
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#define MAX77759_MAXQ_REG_UIC_INT1 0x64
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#define MAX77759_MAXQ_REG_UIC_INT1_APCMDRESI BIT(7)
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#define MAX77759_MAXQ_REG_UIC_INT1_SYSMSGI BIT(6)
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#define MAX77759_MAXQ_REG_UIC_INT1_GPIO6I BIT(1)
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#define MAX77759_MAXQ_REG_UIC_INT1_GPIO5I BIT(0)
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#define MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(offs, en) (((en) & 1) << (offs))
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#define MAX77759_MAXQ_REG_UIC_INT1_GPIOxI_MASK(offs) \
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MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(offs, ~0)
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#define MAX77759_MAXQ_REG_UIC_INT2 0x65
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#define MAX77759_MAXQ_REG_UIC_INT3 0x66
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#define MAX77759_MAXQ_REG_UIC_INT4 0x67
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#define MAX77759_MAXQ_REG_UIC_UIC_STATUS1 0x68
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#define MAX77759_MAXQ_REG_UIC_UIC_STATUS2 0x69
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#define MAX77759_MAXQ_REG_UIC_UIC_STATUS3 0x6a
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#define MAX77759_MAXQ_REG_UIC_UIC_STATUS4 0x6b
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#define MAX77759_MAXQ_REG_UIC_UIC_STATUS5 0x6c
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#define MAX77759_MAXQ_REG_UIC_UIC_STATUS6 0x6d
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#define MAX77759_MAXQ_REG_UIC_UIC_STATUS7 0x6f
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#define MAX77759_MAXQ_REG_UIC_UIC_STATUS8 0x6f
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#define MAX77759_MAXQ_REG_UIC_INT1_M 0x70
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#define MAX77759_MAXQ_REG_UIC_INT2_M 0x71
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#define MAX77759_MAXQ_REG_UIC_INT3_M 0x72
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#define MAX77759_MAXQ_REG_UIC_INT4_M 0x73
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#define MAX77759_MAXQ_REG_AP_DATAOUT0 0x81
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#define MAX77759_MAXQ_REG_AP_DATAOUT32 0xa1
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#define MAX77759_MAXQ_REG_AP_DATAIN0 0xb1
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#define MAX77759_MAXQ_REG_UIC_SWRST 0xe0
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#define MAX77759_CHGR_REG_CHG_INT 0xb0
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#define MAX77759_CHGR_REG_CHG_INT_AICL BIT(7)
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#define MAX77759_CHGR_REG_CHG_INT_CHGIN BIT(6)
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#define MAX77759_CHGR_REG_CHG_INT_WCIN BIT(5)
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#define MAX77759_CHGR_REG_CHG_INT_CHG BIT(4)
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#define MAX77759_CHGR_REG_CHG_INT_BAT BIT(3)
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#define MAX77759_CHGR_REG_CHG_INT_INLIM BIT(2)
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#define MAX77759_CHGR_REG_CHG_INT_THM2 BIT(1)
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#define MAX77759_CHGR_REG_CHG_INT_BYP BIT(0)
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#define MAX77759_CHGR_REG_CHG_INT2 0xb1
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#define MAX77759_CHGR_REG_CHG_INT2_INSEL BIT(7)
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#define MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1 BIT(6)
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#define MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2 BIT(5)
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#define MAX77759_CHGR_REG_CHG_INT2_BAT_OILO BIT(4)
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#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC BIT(3)
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#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV BIT(2)
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#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO BIT(1)
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#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE BIT(0)
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#define MAX77759_CHGR_REG_CHG_INT_MASK 0xb2
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#define MAX77759_CHGR_REG_CHG_INT2_MASK 0xb3
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#define MAX77759_CHGR_REG_CHG_INT_OK 0xb4
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#define MAX77759_CHGR_REG_CHG_DETAILS_00 0xb5
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#define MAX77759_CHGR_REG_CHG_DETAILS_00_CHGIN_DTLS GENMASK(6, 5)
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#define MAX77759_CHGR_REG_CHG_DETAILS_01 0xb6
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#define MAX77759_CHGR_REG_CHG_DETAILS_01_BAT_DTLS GENMASK(6, 4)
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#define MAX77759_CHGR_REG_CHG_DETAILS_01_CHG_DTLS GENMASK(3, 0)
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#define MAX77759_CHGR_REG_CHG_DETAILS_02 0xb7
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#define MAX77759_CHGR_REG_CHG_DETAILS_02_CHGIN_STS BIT(5)
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#define MAX77759_CHGR_REG_CHG_DETAILS_03 0xb8
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#define MAX77759_CHGR_REG_CHG_CNFG_00 0xb9
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#define MAX77759_CHGR_REG_CHG_CNFG_00_MODE GENMASK(3, 0)
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#define MAX77759_CHGR_REG_CHG_CNFG_01 0xba
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#define MAX77759_CHGR_REG_CHG_CNFG_02 0xbb
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#define MAX77759_CHGR_REG_CHG_CNFG_02_CHGCC GENMASK(5, 0)
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#define MAX77759_CHGR_REG_CHG_CNFG_03 0xbc
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#define MAX77759_CHGR_REG_CHG_CNFG_04 0xbd
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#define MAX77759_CHGR_REG_CHG_CNFG_04_CHG_CV_PRM GENMASK(5, 0)
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#define MAX77759_CHGR_REG_CHG_CNFG_05 0xbe
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#define MAX77759_CHGR_REG_CHG_CNFG_06 0xbf
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#define MAX77759_CHGR_REG_CHG_CNFG_06_CHGPROT GENMASK(3, 2)
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#define MAX77759_CHGR_REG_CHG_CNFG_07 0xc0
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#define MAX77759_CHGR_REG_CHG_CNFG_08 0xc1
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#define MAX77759_CHGR_REG_CHG_CNFG_09 0xc2
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#define MAX77759_CHGR_REG_CHG_CNFG_09_CHGIN_ILIM GENMASK(6, 0)
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#define MAX77759_CHGR_REG_CHG_CNFG_10 0xc3
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#define MAX77759_CHGR_REG_CHG_CNFG_11 0xc4
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#define MAX77759_CHGR_REG_CHG_CNFG_12 0xc5
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/* Wireless Charging input channel select */
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#define MAX77759_CHGR_REG_CHG_CNFG_12_WCINSEL BIT(6)
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/* CHGIN/USB input channel select */
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#define MAX77759_CHGR_REG_CHG_CNFG_12_CHGINSEL BIT(5)
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#define MAX77759_CHGR_REG_CHG_CNFG_13 0xc6
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#define MAX77759_CHGR_REG_CHG_CNFG_14 0xc7
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#define MAX77759_CHGR_REG_CHG_CNFG_15 0xc8
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#define MAX77759_CHGR_REG_CHG_CNFG_16 0xc9
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#define MAX77759_CHGR_REG_CHG_CNFG_17 0xca
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#define MAX77759_CHGR_REG_CHG_CNFG_18 0xcb
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#define MAX77759_CHGR_REG_CHG_CNFG_18_WDTEN BIT(0)
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#define MAX77759_CHGR_REG_CHG_CNFG_19 0xcc
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/* MaxQ opcodes for max77759_maxq_command() */
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#define MAX77759_MAXQ_OPCODE_MAXLENGTH (MAX77759_MAXQ_REG_AP_DATAOUT32 - \
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MAX77759_MAXQ_REG_AP_DATAOUT0 + \
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1)
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#define MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_READ 0x21
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#define MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_WRITE 0x22
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#define MAX77759_MAXQ_OPCODE_GPIO_CONTROL_READ 0x23
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#define MAX77759_MAXQ_OPCODE_GPIO_CONTROL_WRITE 0x24
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#define MAX77759_MAXQ_OPCODE_USER_SPACE_READ 0x81
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#define MAX77759_MAXQ_OPCODE_USER_SPACE_WRITE 0x82
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/**
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* enum max77759_chgr_chgin_dtls_status - Charger Input Status
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* @MAX77759_CHGR_CHGIN_DTLS_VBUS_UNDERVOLTAGE:
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* Charger input voltage (Vchgin) < Under Voltage Threshold (Vuvlo)
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* @MAX77759_CHGR_CHGIN_DTLS_VBUS_MARGINAL_VOLTAGE:
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* Vchgin > Vuvlo and Vchgin < (Battery Voltage (Vbatt) + system voltage (Vsys))
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* @MAX77759_CHGR_CHGIN_DTLS_VBUS_OVERVOLTAGE:
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* Vchgin > Over Voltage threshold (Vovlo)
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* @MAX77759_CHGR_CHGIN_DTLS_VBUS_VALID:
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* Vchgin > Vuvlo, Vchgin < Vovlo and Vchgin > (Vsys + Vbatt)
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*/
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enum max77759_chgr_chgin_dtls_status {
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MAX77759_CHGR_CHGIN_DTLS_VBUS_UNDERVOLTAGE,
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MAX77759_CHGR_CHGIN_DTLS_VBUS_MARGINAL_VOLTAGE,
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MAX77759_CHGR_CHGIN_DTLS_VBUS_OVERVOLTAGE,
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MAX77759_CHGR_CHGIN_DTLS_VBUS_VALID,
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};
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/**
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* enum max77759_chgr_bat_dtls_states - Battery Details
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* @MAX77759_CHGR_BAT_DTLS_NO_BATT_CHG_SUSP: No battery and the charger suspended
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* @MAX77759_CHGR_BAT_DTLS_DEAD_BATTERY: Vbatt < Vtrickle
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* @MAX77759_CHGR_BAT_DTLS_BAT_CHG_TIMER_FAULT: Charging suspended due to timer fault
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* @MAX77759_CHGR_BAT_DTLS_BAT_OKAY: Battery okay and Vbatt > Min Sys Voltage (Vsysmin)
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* @MAX77759_CHGR_BAT_DTLS_BAT_UNDERVOLTAGE: Battery is okay. Vtrickle < Vbatt < Vsysmin
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* @MAX77759_CHGR_BAT_DTLS_BAT_OVERVOLTAGE: Battery voltage > Overvoltage threshold
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* @MAX77759_CHGR_BAT_DTLS_BAT_OVERCURRENT: Battery current exceeds overcurrent threshold
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* @MAX77759_CHGR_BAT_DTLS_BAT_ONLY_MODE: Battery only mode and battery level not available
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*/
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enum max77759_chgr_bat_dtls_states {
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MAX77759_CHGR_BAT_DTLS_NO_BATT_CHG_SUSP,
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MAX77759_CHGR_BAT_DTLS_DEAD_BATTERY,
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MAX77759_CHGR_BAT_DTLS_BAT_CHG_TIMER_FAULT,
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MAX77759_CHGR_BAT_DTLS_BAT_OKAY,
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MAX77759_CHGR_BAT_DTLS_BAT_UNDERVOLTAGE,
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MAX77759_CHGR_BAT_DTLS_BAT_OVERVOLTAGE,
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MAX77759_CHGR_BAT_DTLS_BAT_OVERCURRENT,
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MAX77759_CHGR_BAT_DTLS_BAT_ONLY_MODE,
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};
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/**
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* enum max77759_chgr_chg_dtls_states - Charger Details
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* @MAX77759_CHGR_CHG_DTLS_PREQUAL: Charger in prequalification mode
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* @MAX77759_CHGR_CHG_DTLS_CC: Charger in fast charge const curr mode
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* @MAX77759_CHGR_CHG_DTLS_CV: Charger in fast charge const voltage mode
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* @MAX77759_CHGR_CHG_DTLS_TO: Charger is in top off mode
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* @MAX77759_CHGR_CHG_DTLS_DONE: Charger is done
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* @MAX77759_CHGR_CHG_DTLS_RSVD_1: Reserved
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* @MAX77759_CHGR_CHG_DTLS_TIMER_FAULT: Charger is in timer fault mode
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* @MAX77759_CHGR_CHG_DTLS_SUSP_BATT_THM: Charger is suspended as battery removal detected
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* @MAX77759_CHGR_CHG_DTLS_OFF: Charger is off. Input invalid or charger disabled
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* @MAX77759_CHGR_CHG_DTLS_RSVD_2: Reserved
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* @MAX77759_CHGR_CHG_DTLS_RSVD_3: Reserved
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* @MAX77759_CHGR_CHG_DTLS_OFF_WDOG_TIMER: Charger is off as watchdog timer expired
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* @MAX77759_CHGR_CHG_DTLS_SUSP_JEITA: Charger is in JEITA control mode
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*/
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enum max77759_chgr_chg_dtls_states {
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MAX77759_CHGR_CHG_DTLS_PREQUAL,
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MAX77759_CHGR_CHG_DTLS_CC,
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MAX77759_CHGR_CHG_DTLS_CV,
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MAX77759_CHGR_CHG_DTLS_TO,
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MAX77759_CHGR_CHG_DTLS_DONE,
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MAX77759_CHGR_CHG_DTLS_RSVD_1,
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MAX77759_CHGR_CHG_DTLS_TIMER_FAULT,
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MAX77759_CHGR_CHG_DTLS_SUSP_BATT_THM,
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MAX77759_CHGR_CHG_DTLS_OFF,
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MAX77759_CHGR_CHG_DTLS_RSVD_2,
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MAX77759_CHGR_CHG_DTLS_RSVD_3,
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MAX77759_CHGR_CHG_DTLS_OFF_WDOG_TIMER,
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MAX77759_CHGR_CHG_DTLS_SUSP_JEITA,
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};
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enum max77759_chgr_mode {
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MAX77759_CHGR_MODE_OFF,
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MAX77759_CHGR_MODE_CHG_BUCK_ON = 0x5,
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MAX77759_CHGR_MODE_OTG_BOOST_ON = 0xA,
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};
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/**
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* struct max77759 - core max77759 internal data structure
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*
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* @regmap_top: Regmap for accessing TOP registers
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* @maxq_lock: Lock for serializing access to MaxQ
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* @regmap_maxq: Regmap for accessing MaxQ registers
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* @cmd_done: Used to signal completion of a MaxQ command
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* @regmap_charger: Regmap for accessing charger registers
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*
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* The MAX77759 comprises several sub-blocks, namely TOP, MaxQ, Charger,
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* Fuel Gauge, and TCPCI.
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*/
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struct max77759 {
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struct regmap *regmap_top;
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/* This protects MaxQ commands - only one can be active */
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struct mutex maxq_lock;
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struct regmap *regmap_maxq;
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struct completion cmd_done;
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struct regmap *regmap_charger;
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};
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/**
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* struct max77759_maxq_command - structure containing the MaxQ command to
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* send
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*
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* @length: The number of bytes to send.
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* @cmd: The data to send.
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*/
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struct max77759_maxq_command {
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u8 length;
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u8 cmd[] __counted_by(length);
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};
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/**
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* struct max77759_maxq_response - structure containing the MaxQ response
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*
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* @length: The number of bytes to receive.
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* @rsp: The data received. Must have at least @length bytes space.
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*/
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struct max77759_maxq_response {
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u8 length;
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u8 rsp[] __counted_by(length);
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};
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/**
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* max77759_maxq_command() - issue a MaxQ command and wait for the response
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* and associated data
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*
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* @max77759: The core max77759 device handle.
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* @cmd: The command to be sent.
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* @rsp: Any response data associated with the command will be copied here;
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* can be %NULL if the command has no response (other than ACK).
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*
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* Return: 0 on success, a negative error number otherwise.
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*/
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int max77759_maxq_command(struct max77759 *max77759,
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const struct max77759_maxq_command *cmd,
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struct max77759_maxq_response *rsp);
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#endif /* __LINUX_MFD_MAX77759_H */
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