mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-03-03 18:28:01 +01:00
The Rust kernel code should be kept `rustdoc`-clean [1].
Our custom `srctree` link checker in the `rustdoc` target reports:
warning: srctree/ link to include/io-pgtable.h does not exist
Thus fix it.
Link: https://rust-for-linux.com/contributing#submit-checklist-addendum [1]
Fixes: 2e2f6b0ef8 ("rust: iommu: add io_pgtable abstraction")
Signed-off-by: Miguel Ojeda <ojeda@kernel.org>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
280 lines
9.5 KiB
Rust
280 lines
9.5 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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//! IOMMU page table management.
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//!
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//! C header: [`include/linux/io-pgtable.h`](srctree/include/linux/io-pgtable.h)
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use core::{
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marker::PhantomData,
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ptr::NonNull, //
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};
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use crate::{
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alloc,
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bindings,
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device::{
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Bound,
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Device, //
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},
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devres::Devres,
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error::to_result,
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io::PhysAddr,
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prelude::*, //
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};
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use bindings::io_pgtable_fmt;
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/// Protection flags used with IOMMU mappings.
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pub mod prot {
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/// Read access.
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pub const READ: u32 = bindings::IOMMU_READ;
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/// Write access.
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pub const WRITE: u32 = bindings::IOMMU_WRITE;
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/// Request cache coherency.
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pub const CACHE: u32 = bindings::IOMMU_CACHE;
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/// Request no-execute permission.
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pub const NOEXEC: u32 = bindings::IOMMU_NOEXEC;
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/// MMIO peripheral mapping.
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pub const MMIO: u32 = bindings::IOMMU_MMIO;
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/// Privileged mapping.
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pub const PRIVILEGED: u32 = bindings::IOMMU_PRIV;
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}
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/// Represents a requested `io_pgtable` configuration.
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pub struct Config {
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/// Quirk bitmask (type-specific).
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pub quirks: usize,
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/// Valid page sizes, as a bitmask of powers of two.
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pub pgsize_bitmap: usize,
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/// Input address space size in bits.
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pub ias: u32,
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/// Output address space size in bits.
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pub oas: u32,
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/// IOMMU uses coherent accesses for page table walks.
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pub coherent_walk: bool,
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}
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/// An io page table using a specific format.
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///
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/// # Invariants
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///
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/// The pointer references a valid io page table.
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pub struct IoPageTable<F: IoPageTableFmt> {
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ptr: NonNull<bindings::io_pgtable_ops>,
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_marker: PhantomData<F>,
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}
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// SAFETY: `struct io_pgtable_ops` is not restricted to a single thread.
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unsafe impl<F: IoPageTableFmt> Send for IoPageTable<F> {}
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// SAFETY: `struct io_pgtable_ops` may be accessed concurrently.
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unsafe impl<F: IoPageTableFmt> Sync for IoPageTable<F> {}
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/// The format used by this page table.
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pub trait IoPageTableFmt: 'static {
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/// The value representing this format.
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const FORMAT: io_pgtable_fmt;
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}
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impl<F: IoPageTableFmt> IoPageTable<F> {
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/// Create a new `IoPageTable` as a device resource.
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#[inline]
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pub fn new(
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dev: &Device<Bound>,
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config: Config,
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) -> impl PinInit<Devres<IoPageTable<F>>, Error> + '_ {
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// SAFETY: Devres ensures that the value is dropped during device unbind.
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Devres::new(dev, unsafe { Self::new_raw(dev, config) })
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}
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/// Create a new `IoPageTable`.
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///
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/// # Safety
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///
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/// If successful, then the returned `IoPageTable` must be dropped before the device is
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/// unbound.
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#[inline]
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pub unsafe fn new_raw(dev: &Device<Bound>, config: Config) -> Result<IoPageTable<F>> {
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let mut raw_cfg = bindings::io_pgtable_cfg {
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quirks: config.quirks,
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pgsize_bitmap: config.pgsize_bitmap,
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ias: config.ias,
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oas: config.oas,
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coherent_walk: config.coherent_walk,
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tlb: &raw const NOOP_FLUSH_OPS,
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iommu_dev: dev.as_raw(),
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// SAFETY: All zeroes is a valid value for `struct io_pgtable_cfg`.
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..unsafe { core::mem::zeroed() }
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};
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// SAFETY:
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// * The raw_cfg pointer is valid for the duration of this call.
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// * The provided `FLUSH_OPS` contains valid function pointers that accept a null pointer
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// as cookie.
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// * The caller ensures that the io pgtable does not outlive the device.
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let ops = unsafe {
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bindings::alloc_io_pgtable_ops(F::FORMAT, &mut raw_cfg, core::ptr::null_mut())
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};
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// INVARIANT: We successfully created a valid page table.
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Ok(IoPageTable {
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ptr: NonNull::new(ops).ok_or(ENOMEM)?,
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_marker: PhantomData,
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})
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}
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/// Obtain a raw pointer to the underlying `struct io_pgtable_ops`.
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#[inline]
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pub fn raw_ops(&self) -> *mut bindings::io_pgtable_ops {
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self.ptr.as_ptr()
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}
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/// Obtain a raw pointer to the underlying `struct io_pgtable`.
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#[inline]
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pub fn raw_pgtable(&self) -> *mut bindings::io_pgtable {
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// SAFETY: The io_pgtable_ops of an io-pgtable is always the ops field of a io_pgtable.
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unsafe { kernel::container_of!(self.raw_ops(), bindings::io_pgtable, ops) }
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}
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/// Obtain a raw pointer to the underlying `struct io_pgtable_cfg`.
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#[inline]
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pub fn raw_cfg(&self) -> *mut bindings::io_pgtable_cfg {
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// SAFETY: The `raw_pgtable()` method returns a valid pointer.
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unsafe { &raw mut (*self.raw_pgtable()).cfg }
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}
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/// Map a physically contiguous range of pages of the same size.
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///
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/// Even if successful, this operation may not map the entire range. In that case, only a
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/// prefix of the range is mapped, and the returned integer indicates its length in bytes. In
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/// this case, the caller will usually call `map_pages` again for the remaining range.
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///
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/// The returned [`Result`] indicates whether an error was encountered while mapping pages.
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/// Note that this may return a non-zero length even if an error was encountered. The caller
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/// will usually [unmap the relevant pages](Self::unmap_pages) on error.
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///
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/// The caller must flush the TLB before using the pgtable to access the newly created mapping.
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///
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/// # Safety
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///
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/// * No other io-pgtable operation may access the range `iova .. iova+pgsize*pgcount` while
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/// this `map_pages` operation executes.
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/// * This page table must not contain any mapping that overlaps with the mapping created by
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/// this call.
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/// * If this page table is live, then the caller must ensure that it's okay to access the
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/// physical address being mapped for the duration in which it is mapped.
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#[inline]
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pub unsafe fn map_pages(
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&self,
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iova: usize,
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paddr: PhysAddr,
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pgsize: usize,
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pgcount: usize,
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prot: u32,
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flags: alloc::Flags,
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) -> (usize, Result) {
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let mut mapped: usize = 0;
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// SAFETY: The `map_pages` function in `io_pgtable_ops` is never null.
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let map_pages = unsafe { (*self.raw_ops()).map_pages.unwrap_unchecked() };
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// SAFETY: The safety requirements of this method are sufficient to call `map_pages`.
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let ret = to_result(unsafe {
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(map_pages)(
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self.raw_ops(),
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iova,
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paddr,
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pgsize,
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pgcount,
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prot as i32,
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flags.as_raw(),
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&mut mapped,
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)
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});
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(mapped, ret)
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}
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/// Unmap a range of virtually contiguous pages of the same size.
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///
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/// This may not unmap the entire range, and returns the length of the unmapped prefix in
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/// bytes.
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///
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/// # Safety
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///
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/// * No other io-pgtable operation may access the range `iova .. iova+pgsize*pgcount` while
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/// this `unmap_pages` operation executes.
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/// * This page table must contain one or more consecutive mappings starting at `iova` whose
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/// total size is `pgcount * pgsize`.
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#[inline]
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#[must_use]
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pub unsafe fn unmap_pages(&self, iova: usize, pgsize: usize, pgcount: usize) -> usize {
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// SAFETY: The `unmap_pages` function in `io_pgtable_ops` is never null.
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let unmap_pages = unsafe { (*self.raw_ops()).unmap_pages.unwrap_unchecked() };
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// SAFETY: The safety requirements of this method are sufficient to call `unmap_pages`.
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unsafe { (unmap_pages)(self.raw_ops(), iova, pgsize, pgcount, core::ptr::null_mut()) }
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}
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}
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// For the initial users of these rust bindings, the GPU FW is managing the IOTLB and performs all
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// required invalidations using a range. There is no need for it get ARM style invalidation
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// instructions from the page table code.
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//
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// Support for flushing the TLB with ARM style invalidation instructions may be added in the
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// future.
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static NOOP_FLUSH_OPS: bindings::iommu_flush_ops = bindings::iommu_flush_ops {
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tlb_flush_all: Some(rust_tlb_flush_all_noop),
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tlb_flush_walk: Some(rust_tlb_flush_walk_noop),
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tlb_add_page: None,
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};
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#[no_mangle]
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extern "C" fn rust_tlb_flush_all_noop(_cookie: *mut core::ffi::c_void) {}
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#[no_mangle]
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extern "C" fn rust_tlb_flush_walk_noop(
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_iova: usize,
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_size: usize,
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_granule: usize,
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_cookie: *mut core::ffi::c_void,
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) {
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}
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impl<F: IoPageTableFmt> Drop for IoPageTable<F> {
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fn drop(&mut self) {
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// SAFETY: The caller of `Self::ttbr()` promised that the page table is not live when this
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// destructor runs.
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unsafe { bindings::free_io_pgtable_ops(self.raw_ops()) };
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}
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}
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/// The `ARM_64_LPAE_S1` page table format.
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pub enum ARM64LPAES1 {}
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impl IoPageTableFmt for ARM64LPAES1 {
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const FORMAT: io_pgtable_fmt = bindings::io_pgtable_fmt_ARM_64_LPAE_S1 as io_pgtable_fmt;
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}
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impl IoPageTable<ARM64LPAES1> {
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/// Access the `ttbr` field of the configuration.
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///
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/// This is the physical address of the page table, which may be passed to the device that
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/// needs to use it.
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///
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/// # Safety
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///
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/// The caller must ensure that the device stops using the page table before dropping it.
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#[inline]
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pub unsafe fn ttbr(&self) -> u64 {
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// SAFETY: `arm_lpae_s1_cfg` is the right cfg type for `ARM64LPAES1`.
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unsafe { (*self.raw_cfg()).__bindgen_anon_1.arm_lpae_s1_cfg.ttbr }
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}
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/// Access the `mair` field of the configuration.
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#[inline]
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pub fn mair(&self) -> u64 {
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// SAFETY: `arm_lpae_s1_cfg` is the right cfg type for `ARM64LPAES1`.
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unsafe { (*self.raw_cfg()).__bindgen_anon_1.arm_lpae_s1_cfg.mair }
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}
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}
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