Stefan Agner 09c8192be7 mmc: sdhci-esdhc-imx: support eMMC DDR mode when running at 3.3V ...

The uSDHC supports DDR modes for eMMC devices running at 3.3V. This
allows to run eMMC with 3.3V signaling voltage at DDR52 mode:

  # cat /sys/kernel/debug/mmc1/ios
  clock:          52000000 Hz
  vdd:            21 (3.3 ~ 3.4 V)
  bus mode:       2 (push-pull)
  chip select:    0 (don't care)
  power mode:     2 (on)
  bus width:      3 (8 bits)
  timing spec:    8 (mmc DDR52)
  signal voltage: 0 (3.30 V)
  driver type:    0 (driver type B)

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

2018-07-16 11:21:45 +02:00

..

core

mmc: core: Drop the unused mmc_power_save|restore_host()

2018-07-16 11:21:45 +02:00

host

mmc: sdhci-esdhc-imx: support eMMC DDR mode when running at 3.3V

2018-07-16 11:21:45 +02:00

Kconfig

mmc: core: Remove option not to use blk-mq

2017-12-11 12:55:02 +01:00

Makefile

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