Avadhut Naik d0564ab15d x86/mce: Do not clear bank's poll bit in mce_poll_banks on AMD SMCA systems ...

commit d7ac083f09 upstream.

Currently, when a CMCI storm detected on a Machine Check bank, subsides, the
bank's corresponding bit in the mce_poll_banks per-CPU variable is cleared
unconditionally by cmci_storm_end().

On AMD SMCA systems, this essentially disables polling on that particular bank
on that CPU. Consequently, any subsequent correctable errors or storms will not
be logged.

Since AMD SMCA systems allow banks to be managed by both polling and
interrupts, the polling banks bitmap for a CPU, i.e., mce_poll_banks, should
not be modified when a storm subsides.

Fixes: 7eae17c4ad ("x86/mce: Add per-bank CMCI storm mitigation")
Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251121190542.2447913-2-avadhut.naik@amd.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2026-01-08 10:14:13 +01:00

..

amd.c

x86/mce/amd: Fix threshold limit reset

2025-07-17 18:37:07 +02:00

apei.c

…

core.c

x86/mce: Ensure user polling settings are honored when restarting timer

2025-07-17 18:37:08 +02:00

dev-mcelog.c

…

genpool.c

…

inject.c

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intel.c

x86/mce: Make sure CMCI banks are cleared during shutdown on Intel

2025-07-17 18:37:08 +02:00

internal.h

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Makefile

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p5.c

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severity.c

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threshold.c

x86/mce: Do not clear bank's poll bit in mce_poll_banks on AMD SMCA systems

2026-01-08 10:14:13 +01:00

winchip.c

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