Alok Tiwari 28defa35ed clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver ...

[ Upstream commit 1624dead9a ]

The conditional check for the PLL0 multiplier 'm' used a logical AND
instead of OR, making the range check ineffective. This patch replaces
&& with || to correctly reject invalid values of 'm' that are either
less than or equal to 0 or greater than LPC18XX_PLL0_MSEL_MAX.

This ensures proper bounds checking during clk rate setting and rounding.

Fixes: b04e0b8fd5 ("clk: add lpc18xx cgu clk driver")
Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
[sboyd@kernel.org: 'm' is unsigned so remove < condition]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2025-10-19 16:33:38 +02:00

..

clk-lpc18xx-ccu.c

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clk-lpc18xx-cgu.c

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clk-lpc18xx-creg.c

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clk-lpc32xx.c

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Makefile

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