Chris Brandt 47671671a3 clk: renesas: rzg2l: Select correct div round macro ...

[ Upstream commit f9451374dc ]

Variable foutvco_rate is an unsigned long, not an unsigned long long.

Cc: stable@kernel.org
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Closes: https://lore.kernel.org/CAMuHMdVf7dSeqAhtyxDCFuCheQRzwS-8996Rr2Ntui21uiBgdA@mail.gmail.com
Fixes: dabf72b85f ("clk: renesas: rzg2l: Fix FOUTPOSTDIV clk")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251114194529.3304361-1-chris.brandt@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2026-03-04 07:21:36 -05:00

..

clk-div6.c

…

clk-div6.h

…

clk-emev2.c

…

clk-mstp.c

…

clk-r8a73a4.c

…

clk-r8a7740.c

…

clk-r8a7778.c

…

clk-r8a7779.c

…

clk-rz.c

…

clk-sh73a0.c

…

Kconfig

…

Makefile

…

r7s9210-cpg-mssr.c

clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register

2025-12-18 13:54:41 +01:00

r8a774a1-cpg-mssr.c

…

r8a774b1-cpg-mssr.c

…

r8a774c0-cpg-mssr.c

…

r8a774e1-cpg-mssr.c

…

r8a779a0-cpg-mssr.c

…

r8a779f0-cpg-mssr.c

…

r8a779g0-cpg-mssr.c

…

r8a779h0-cpg-mssr.c

…

r8a7742-cpg-mssr.c

…

r8a7743-cpg-mssr.c

…

r8a7745-cpg-mssr.c

…

r8a7790-cpg-mssr.c

…

r8a7791-cpg-mssr.c

…

r8a7792-cpg-mssr.c

…

r8a7794-cpg-mssr.c

…

r8a7795-cpg-mssr.c

…

r8a7796-cpg-mssr.c

…

r8a77470-cpg-mssr.c

…

r8a77965-cpg-mssr.c

…

r8a77970-cpg-mssr.c

clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register

2025-12-18 13:54:41 +01:00

r8a77980-cpg-mssr.c

…

r8a77990-cpg-mssr.c

…

r8a77995-cpg-mssr.c

…

r9a06g032-clocks.c

clk: renesas: r9a06g032: Fix memory leak in error path

2025-12-18 13:54:57 +01:00

r9a07g043-cpg.c

…

r9a07g044-cpg.c

…

r9a08g045-cpg.c

…

r9a09g011-cpg.c

…

r9a09g057-cpg.c

…

rcar-cpg-lib.c

…

rcar-cpg-lib.h

…

rcar-gen2-cpg.c

clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register

2025-12-18 13:54:41 +01:00

rcar-gen2-cpg.h

clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register

2025-12-18 13:54:41 +01:00

rcar-gen3-cpg.c

clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register

2025-12-18 13:54:41 +01:00

rcar-gen3-cpg.h

clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register

2025-12-18 13:54:41 +01:00

rcar-gen4-cpg.c

clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register

2025-12-18 13:54:41 +01:00

rcar-gen4-cpg.h

clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register

2025-12-18 13:54:41 +01:00

rcar-usb2-clock-sel.c

…

renesas-cpg-mssr.c

clk: renesas: cpg-mssr: Read back reset registers to assure values latched

2025-12-18 13:54:41 +01:00

renesas-cpg-mssr.h

clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register

2025-12-18 13:54:41 +01:00

rzg2l-cpg.c

clk: renesas: rzg2l: Select correct div round macro

2026-03-04 07:21:36 -05:00

rzg2l-cpg.h

…

rzv2h-cpg.c

…

rzv2h-cpg.h

…