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commit295f58fdccupstream. As like other SDX SoCs, SDX75 SoC's QPIC BCM resource was modeled as a RPMh clock in clk-rpmh driver. However, for SDX75, this resource was also described as an interconnect and BCM node mistakenly. It is incorrect to describe the same resource in two different providers, as it will lead to votes from clients overriding each other. Hence, drop the QPIC interconnect and BCM nodes and let the clients use clk-rpmh driver to vote for this resource. Without this change, the NAND driver fails to probe on SDX75, as the interconnect sync state disables the QPIC nodes as there were no clients voting for this ICC resource. However, the NAND driver had already voted for this BCM resource through the clk-rpmh driver. Since both votes come from Linux, RPMh was unable to distinguish between these two and ends up disabling the QPIC resource during sync state. Cc: stable@vger.kernel.org Fixes:3642b4e5cb("interconnect: qcom: Add SDX75 interconnect provider driver") Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> [mani: dropped the reference to bcm_qp0, reworded description] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Lakshmi Sowjanya D <quic_laksd@quicinc.com> # on SDX75 Link: https://lore.kernel.org/r/20250926-sdx75-icc-v2-1-20d6820e455c@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
96 lines
3.1 KiB
C
96 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX75_H
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#define __DRIVERS_INTERCONNECT_QCOM_SDX75_H
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#define SDX75_MASTER_ANOC_PCIE_GEM_NOC 0
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#define SDX75_MASTER_ANOC_SNOC 1
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#define SDX75_MASTER_APPSS_PROC 2
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#define SDX75_MASTER_AUDIO 3
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#define SDX75_MASTER_CNOC_DC_NOC 4
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#define SDX75_MASTER_CRYPTO 5
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#define SDX75_MASTER_EMAC_0 6
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#define SDX75_MASTER_EMAC_1 7
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#define SDX75_MASTER_GEM_NOC_CFG 8
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#define SDX75_MASTER_GEM_NOC_CNOC 9
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#define SDX75_MASTER_GEM_NOC_PCIE_SNOC 10
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#define SDX75_MASTER_GIC 11
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#define SDX75_MASTER_GIC_AHB 12
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#define SDX75_MASTER_IPA 13
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#define SDX75_MASTER_IPA_PCIE 14
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#define SDX75_MASTER_LLCC 15
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#define SDX75_MASTER_MSS_PROC 16
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#define SDX75_MASTER_MVMSS 17
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#define SDX75_MASTER_PCIE_0 18
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#define SDX75_MASTER_PCIE_1 19
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#define SDX75_MASTER_PCIE_2 20
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#define SDX75_MASTER_PCIE_ANOC_CFG 21
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#define SDX75_MASTER_PCIE_RSCC 22
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#define SDX75_MASTER_QDSS_BAM 23
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#define SDX75_MASTER_QDSS_ETR 24
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#define SDX75_MASTER_QDSS_ETR_1 25
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#define SDX75_MASTER_QPIC 26
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#define SDX75_MASTER_QUP_0 28
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#define SDX75_MASTER_QUP_CORE_0 29
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#define SDX75_MASTER_SDCC_1 30
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#define SDX75_MASTER_SDCC_4 31
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#define SDX75_MASTER_SNOC_CFG 32
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#define SDX75_MASTER_SNOC_SF_MEM_NOC 33
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#define SDX75_MASTER_SYS_TCU 34
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#define SDX75_MASTER_USB3_0 35
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#define SDX75_SLAVE_A1NOC_CFG 36
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#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 37
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#define SDX75_SLAVE_AUDIO 38
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#define SDX75_SLAVE_CLK_CTL 39
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#define SDX75_SLAVE_CRYPTO_0_CFG 40
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#define SDX75_SLAVE_CNOC_MSS 41
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#define SDX75_SLAVE_DDRSS_CFG 42
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#define SDX75_SLAVE_EBI1 43
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#define SDX75_SLAVE_ETH0_CFG 44
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#define SDX75_SLAVE_ETH1_CFG 45
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#define SDX75_SLAVE_GEM_NOC_CFG 46
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#define SDX75_SLAVE_GEM_NOC_CNOC 47
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#define SDX75_SLAVE_ICBDI_MVMSS_CFG 48
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#define SDX75_SLAVE_IMEM 49
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#define SDX75_SLAVE_IMEM_CFG 50
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#define SDX75_SLAVE_IPA_CFG 51
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#define SDX75_SLAVE_IPC_ROUTER_CFG 52
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#define SDX75_SLAVE_LAGG_CFG 53
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#define SDX75_SLAVE_LLCC 54
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#define SDX75_SLAVE_MCCC_MASTER 55
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#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 56
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#define SDX75_SLAVE_PCIE_0 57
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#define SDX75_SLAVE_PCIE_1 58
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#define SDX75_SLAVE_PCIE_2 59
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#define SDX75_SLAVE_PCIE_0_CFG 60
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#define SDX75_SLAVE_PCIE_1_CFG 61
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#define SDX75_SLAVE_PCIE_2_CFG 62
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#define SDX75_SLAVE_PCIE_ANOC_CFG 63
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#define SDX75_SLAVE_PCIE_RSC_CFG 64
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#define SDX75_SLAVE_PDM 65
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#define SDX75_SLAVE_PRNG 66
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#define SDX75_SLAVE_QDSS_CFG 67
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#define SDX75_SLAVE_QDSS_STM 68
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#define SDX75_SLAVE_QPIC 69
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#define SDX75_SLAVE_QUP_0 71
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#define SDX75_SLAVE_QUP_CORE_0 72
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#define SDX75_SLAVE_SDCC_1 73
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#define SDX75_SLAVE_SDCC_4 74
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#define SDX75_SLAVE_SERVICE_GEM_NOC 75
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#define SDX75_SLAVE_SERVICE_PCIE_ANOC 76
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#define SDX75_SLAVE_SERVICE_SNOC 77
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#define SDX75_SLAVE_SNOC_CFG 78
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#define SDX75_SLAVE_SNOC_GEM_NOC_SF 79
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#define SDX75_SLAVE_SNOOP_BWMON 80
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#define SDX75_SLAVE_SPMI_VGI_COEX 81
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#define SDX75_SLAVE_TCSR 82
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#define SDX75_SLAVE_TCU 83
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#define SDX75_SLAVE_TLMM 84
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#define SDX75_SLAVE_USB3 85
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#define SDX75_SLAVE_USB3_PHY_CFG 86
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#endif
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