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ba7a25411c
[ Upstream commita195c7ccfb] GCE can only fetch the command buffer address from a 32-bit register. Some SoCs support a 35-bit command buffer address for GCE, which requires a right shift of 3 bits before setting the address into the 32-bit register. A comment has been added to the header of cmdq_get_shift_pa() to explain this requirement. To prevent the GCE command buffer address from being DMA mapped beyond its supported bit range, the DMA bit mask for the device is set during initialization. Additionally, to ensure the correct shift is applied when setting or reading the register that stores the GCE command buffer address, new APIs, cmdq_convert_gce_addr() and cmdq_revert_gce_addr(), have been introduced for consistent operations on this register. The variable type for the command buffer address has been standardized to dma_addr_t to prevent handling issues caused by type mismatches. Fixes:0858fde496("mailbox: cmdq: variablize address shift in platform") Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
94 lines
2.2 KiB
C
94 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 MediaTek Inc.
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*
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*/
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#ifndef __MTK_CMDQ_MAILBOX_H__
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#define __MTK_CMDQ_MAILBOX_H__
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#define CMDQ_INST_SIZE 8 /* instruction is 64-bit */
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#define CMDQ_SUBSYS_SHIFT 16
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#define CMDQ_OP_CODE_SHIFT 24
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#define CMDQ_JUMP_PASS CMDQ_INST_SIZE
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#define CMDQ_WFE_UPDATE BIT(31)
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#define CMDQ_WFE_UPDATE_VALUE BIT(16)
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#define CMDQ_WFE_WAIT BIT(15)
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#define CMDQ_WFE_WAIT_VALUE 0x1
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/*
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* WFE arg_b
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* bit 0-11: wait value
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* bit 15: 1 - wait, 0 - no wait
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* bit 16-27: update value
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* bit 31: 1 - update, 0 - no update
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*/
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#define CMDQ_WFE_OPTION (CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE)
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/** cmdq event maximum */
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#define CMDQ_MAX_EVENT 0x3ff
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/*
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* CMDQ_CODE_MASK:
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* set write mask
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* format: op mask
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* CMDQ_CODE_WRITE:
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* write value into target register
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* format: op subsys address value
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* CMDQ_CODE_JUMP:
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* jump by offset
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* format: op offset
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* CMDQ_CODE_WFE:
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* wait for event and clear
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* it is just clear if no wait
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* format: [wait] op event update:1 to_wait:1 wait:1
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* [clear] op event update:1 to_wait:0 wait:0
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* CMDQ_CODE_EOC:
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* end of command
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* format: op irq_flag
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*/
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enum cmdq_code {
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CMDQ_CODE_MASK = 0x02,
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CMDQ_CODE_WRITE = 0x04,
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CMDQ_CODE_POLL = 0x08,
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CMDQ_CODE_JUMP = 0x10,
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CMDQ_CODE_WFE = 0x20,
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CMDQ_CODE_EOC = 0x40,
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CMDQ_CODE_READ_S = 0x80,
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CMDQ_CODE_WRITE_S = 0x90,
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CMDQ_CODE_WRITE_S_MASK = 0x91,
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CMDQ_CODE_LOGIC = 0xa0,
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};
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struct cmdq_cb_data {
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int sta;
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struct cmdq_pkt *pkt;
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};
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struct cmdq_pkt {
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void *va_base;
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dma_addr_t pa_base;
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size_t cmd_buf_size; /* command occupied size */
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size_t buf_size; /* real buffer size */
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void *cl;
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};
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/**
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* cmdq_get_shift_pa() - get the shift bits of physical address
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* @chan: mailbox channel
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*
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* GCE can only fetch the command buffer address from a 32-bit register.
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* Some SOCs support more than 32-bit command buffer address for GCE, which
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* requires some shift bits to make the address fit into the 32-bit register.
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*
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* Return: the shift bits of physical address
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*/
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u8 cmdq_get_shift_pa(struct mbox_chan *chan);
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#endif /* __MTK_CMDQ_MAILBOX_H__ */
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