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985c2c69a5
[ Upstream commit 91b98d5a6e ]
Stress testing resume from suspend on Valve Steam Deck OLED (Galileo)
revealed that the DSP firmware could enter an unrecoverable faulty
state, where the kernel ring buffer is flooded with IPC related error
messages:
[ +0.017002] snd_sof_amd_vangogh 0000:04:00.5: acp_sof_ipc_send_msg: Failed to acquire HW lock
[ +0.000054] snd_sof_amd_vangogh 0000:04:00.5: ipc3_tx_msg_unlocked: ipc message send for 0x30100000 failed: -22
[ +0.000005] snd_sof_amd_vangogh 0000:04:00.5: Failed to setup widget PIPELINE.6.ACPHS1.IN
[ +0.000004] snd_sof_amd_vangogh 0000:04:00.5: Failed to restore pipeline after resume -22
[ +0.000003] snd_sof_amd_vangogh 0000:04:00.5: PM: dpm_run_callback(): pci_pm_resume returns -22
[ +0.000009] snd_sof_amd_vangogh 0000:04:00.5: PM: failed to resume async: error -22
[...]
[ +0.002582] PM: suspend exit
[ +0.065085] snd_sof_amd_vangogh 0000:04:00.5: ipc tx error for 0x30130000 (msg/reply size: 12/0): -22
[ +0.000499] snd_sof_amd_vangogh 0000:04:00.5: error: failed widget list set up for pcm 1 dir 0
[ +0.000011] snd_sof_amd_vangogh 0000:04:00.5: error: set pcm hw_params after resume
[ +0.000006] snd_sof_amd_vangogh 0000:04:00.5: ASoC: error at snd_soc_pcm_component_prepare on 0000:04:00.5: -22
[...]
A system reboot would be necessary to restore the speakers
functionality.
However, by delaying a bit any host to DSP transmission right after
the firmware boot completed, the issue could not be reproduced anymore
and sound continued to work flawlessly even after performing thousands
of suspend/resume cycles.
Introduce the post_fw_run_delay ACP quirk to allow providing the
aforementioned delay via the snd_sof_dsp_ops->post_fw_run() callback for
the affected devices.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://patch.msgid.link/20250207-sof-vangogh-fixes-v1-1-67824c1e4c9a@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
182 lines
4.7 KiB
C
182 lines
4.7 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2023 Advanced Micro Devices, Inc.
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//
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// Authors: Venkata Prasad Potturu <venkataprasad.potturu@amd.com>
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/*
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* Hardware interface for Audio DSP on Vangogh platform
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*/
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include "../ops.h"
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#include "../sof-audio.h"
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#include "acp.h"
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#include "acp-dsp-offset.h"
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#define I2S_HS_INSTANCE 0
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#define I2S_BT_INSTANCE 1
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#define I2S_SP_INSTANCE 2
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#define PDM_DMIC_INSTANCE 3
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#define I2S_HS_VIRTUAL_INSTANCE 4
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static struct snd_soc_dai_driver vangogh_sof_dai[] = {
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[I2S_HS_INSTANCE] = {
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.id = I2S_HS_INSTANCE,
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.name = "acp-sof-hs",
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.playback = {
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
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.channels_min = 2,
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.channels_max = 8,
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.rate_min = 8000,
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.rate_max = 96000,
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},
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.capture = {
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
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/* Supporting only stereo for I2S HS controller capture */
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.channels_min = 2,
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.channels_max = 2,
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.rate_min = 8000,
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.rate_max = 48000,
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},
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},
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[I2S_BT_INSTANCE] = {
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.id = I2S_BT_INSTANCE,
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.name = "acp-sof-bt",
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.playback = {
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
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.channels_min = 2,
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.channels_max = 8,
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.rate_min = 8000,
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.rate_max = 96000,
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},
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.capture = {
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
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/* Supporting only stereo for I2S BT controller capture */
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.channels_min = 2,
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.channels_max = 2,
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.rate_min = 8000,
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.rate_max = 48000,
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},
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},
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[I2S_SP_INSTANCE] = {
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.id = I2S_SP_INSTANCE,
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.name = "acp-sof-sp",
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.playback = {
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
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.channels_min = 2,
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.channels_max = 8,
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.rate_min = 8000,
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.rate_max = 96000,
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},
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.capture = {
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
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/* Supporting only stereo for I2S SP controller capture */
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.channels_min = 2,
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.channels_max = 2,
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.rate_min = 8000,
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.rate_max = 48000,
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},
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},
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[PDM_DMIC_INSTANCE] = {
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.id = PDM_DMIC_INSTANCE,
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.name = "acp-sof-dmic",
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.capture = {
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S32_LE,
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.channels_min = 2,
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.channels_max = 4,
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.rate_min = 8000,
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.rate_max = 48000,
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},
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},
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[I2S_HS_VIRTUAL_INSTANCE] = {
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.id = I2S_HS_VIRTUAL_INSTANCE,
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.name = "acp-sof-hs-virtual",
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.playback = {
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
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.channels_min = 2,
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.channels_max = 8,
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.rate_min = 8000,
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.rate_max = 96000,
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},
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.capture = {
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
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/* Supporting only stereo for I2S HS-Virtual controller capture */
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.channels_min = 2,
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.channels_max = 2,
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.rate_min = 8000,
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.rate_max = 48000,
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},
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},
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};
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static int sof_vangogh_post_fw_run_delay(struct snd_sof_dev *sdev)
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{
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/*
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* Resuming from suspend in some cases my cause the DSP firmware
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* to enter an unrecoverable faulty state. Delaying a bit any host
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* to DSP transmission right after firmware boot completion seems
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* to resolve the issue.
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*/
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if (!sdev->first_boot)
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usleep_range(100, 150);
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return 0;
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}
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/* Vangogh ops */
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struct snd_sof_dsp_ops sof_vangogh_ops;
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EXPORT_SYMBOL_NS(sof_vangogh_ops, SND_SOC_SOF_AMD_COMMON);
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int sof_vangogh_ops_init(struct snd_sof_dev *sdev)
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{
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const struct dmi_system_id *dmi_id;
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struct acp_quirk_entry *quirks;
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/* common defaults */
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memcpy(&sof_vangogh_ops, &sof_acp_common_ops, sizeof(struct snd_sof_dsp_ops));
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sof_vangogh_ops.drv = vangogh_sof_dai;
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sof_vangogh_ops.num_drv = ARRAY_SIZE(vangogh_sof_dai);
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dmi_id = dmi_first_match(acp_sof_quirk_table);
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if (dmi_id) {
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quirks = dmi_id->driver_data;
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if (quirks->signed_fw_image)
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sof_vangogh_ops.load_firmware = acp_sof_load_signed_firmware;
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if (quirks->post_fw_run_delay)
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sof_vangogh_ops.post_fw_run = sof_vangogh_post_fw_run_delay;
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}
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return 0;
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}
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