Ville Syrjälä 141b954cae drm/i915/dmc: Define flip queue related PIPEDMC registers ...

Add the register definitions for a bunch of flip queue related
PIPEDMC registers.

v2: The layout of flip queue entries changed on PTL
    Bump the DMC_FQ_W2_PTS_CFG_SEL bitfields sizes (Uma)
    Reduce the scanlines to 21 bits for now (Uma)
v3: Also define some undocumented DMC variables we need on PTL
v3: Drop PIPEDMC_FQ_CTRL_BUSY as it seems to no longer exist
    on LNL+
    Fix up some typos

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250624170049.27284-4-ville.syrjala@linux.intel.com

2025-06-27 15:54:35 +03:00

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drm

drm/i915/dmc: Define flip queue related PIPEDMC registers

2025-06-27 15:54:35 +03:00

host1x

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ipu-v3

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nova-core

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trace

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vga

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Makefile

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