mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-08-09 06:14:34 +02:00
Ryan ChenandArnd Bergmann
e77bb5dc57
Add initial device tree support for the ASPEED AST27xx family, the 8th-generation Baseboard Management Controller (BMC) SoCs. AST27xx SOC Family - https://www.aspeedtech.com/server_ast2700/ - https://www.aspeedtech.com/server_ast2720/ - https://www.aspeedtech.com/server_ast2750/ The AST27xx features a dual-SoC architecture consisting of two dies, referred to as SoC0 and SoC1 - interconnected through an internal proprietary bus. Both SoCs share the same address decoding scheme, while each maintains independent clock and reset domains. - SoC0 (CPU die): contains a quad-core Cortex-A35 cluster and two Cortex-M4 cores, along with high-speed peripherals. - SoC1 (I/O die): includes the BootMCU (responsible for system boot) and its own clock/reset domains low-speed peripherals. The device tree describes the SoC0 and SoC1 domains and their peripheral layouts. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Link: https://lore.kernel.org/r/20260609-upstream_ast2700-v9-3-f631752f0cb1@aspeedtech.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
43 lines
812 B
Makefile
43 lines
812 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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subdir-y += actions
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subdir-y += airoha
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subdir-y += allwinner
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subdir-y += altera
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subdir-y += amazon
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subdir-y += amd
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subdir-y += amlogic
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subdir-y += apm
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subdir-y += apple
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subdir-y += arm
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subdir-y += aspeed
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subdir-y += axiado
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subdir-y += bitmain
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subdir-y += blaize
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subdir-y += broadcom
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subdir-y += bst
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subdir-y += cavium
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subdir-y += cix
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subdir-y += exynos
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subdir-y += freescale
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subdir-y += hisilicon
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subdir-y += intel
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subdir-y += lg
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subdir-y += marvell
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subdir-y += mediatek
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subdir-y += microchip
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subdir-y += nuvoton
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subdir-y += nvidia
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subdir-y += qcom
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subdir-y += realtek
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subdir-y += renesas
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subdir-y += rockchip
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subdir-y += socionext
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subdir-y += sophgo
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subdir-y += sprd
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subdir-y += st
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subdir-y += synaptics
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subdir-y += tesla
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subdir-y += ti
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subdir-y += toshiba
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subdir-y += xilinx
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