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Devin LiandPeter Chen
89d0ad7f3a
Add PSCI-based CPU idle state definitions for the Sky1 SoC, enabling core and cluster level power management through ARM PSCI firmware. Three idle states are defined: - CPU_SLEEP_0: Core idle state for A520 cores (psci-suspend-param 0x0010000), entry-latency 34us, exit-latency 100us - CPU_SLEEP_1: Core idle state for A720 cores (psci-suspend-param 0x10000), entry-latency 31us, exit-latency 79us - CLUSTER_SLEEP_0: Cluster idle state shared by all cores (psci-suspend-param 0x1010000), entry-latency 41us, exit-latency 104us A520 cores (cpu0-3) reference CPU_SLEEP_0 and CLUSTER_SLEEP_0, while A720 cores (cpu4-11) reference CPU_SLEEP_1 and CLUSTER_SLEEP_0. Signed-off-by: Devin Li <Devin.Li@cixtech.com> Link: https://lore.kernel.org/r/20260507065956.3900087-1-Devin.Li@cixtech.com Signed-off-by: Peter Chen <peter.chen@cixtech.com>