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Nazim AmirulandDinh Nguyen
c5637e5ceb
The Agilex5 SoC provides RGMII TX/RX clock delay compensation through its integrated I/O hardware. Using phy-mode = "rgmii-id" instructs the MAC driver to additionally insert internal TX/RX delays, resulting in double delay being applied and causing Ethernet link timing issues. Change phy-mode to "rgmii" across all Agilex5 device tree files to reflect that the clock delay is already handled by the hardware and no additional software-inserted delay is required. Add an inline comment to satisfy checkpatch and document the hardware-provided delay. Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>