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Catalin MarinasandWill Deacon
534eb6940a
The C1-Pro SME DVMSync workaround currently samples mm_cpumask() from
arch_tlbbatch_add_pending(). It requires a DSB after every batched TLBI
so that the mask read is ordered after the hardware DVMSync, defeating
much of the reclaim batching benefit.
Introduce the sme_active_cpus mask tracking which CPUs run in user-space
with SME enabled and use it for batch flushing instead of accumulating
the mm_cpumask() of the unmapped pages.
Fixes: 0baba94a97 ("arm64: errata: Work around early CME DVMSync acknowledgement")
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Tested-by: Joshua Liu <josliu@google.com>
Signed-off-by: Will Deacon <will@kernel.org>
13 lines
285 B
C
13 lines
285 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ARCH_ARM64_TLBBATCH_H
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#define _ARCH_ARM64_TLBBATCH_H
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struct arch_tlbflush_unmap_batch {
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/*
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* For arm64, HW can do TLB shootdown, so we don't need to record a
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* cpumask for sending IPIs.
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*/
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};
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#endif /* _ARCH_ARM64_TLBBATCH_H */
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