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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-08-09 06:14:34 +02:00
Bibo MaoandHuacai Chen
3179253ad5
With bitmask method, interrupts can be injected with batch mode rather than one by one. Also remove unused array priority_to_irq[] here. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
148 lines
3.5 KiB
C
148 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2023 Loongson Technology Corporation Limited
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*/
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <asm/kvm_csr.h>
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#include <asm/kvm_vcpu.h>
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#include <asm/kvm_dmsintc.h>
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static void kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned long mask)
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{
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unsigned long irq;
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unsigned long old, new;
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if (mask & CPU_AVEC)
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dmsintc_inject_irq(vcpu);
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irq = mask & KVM_ESTAT_INTI_MASK;
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if (irq) {
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old = kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL);
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set_gcsr_estat(irq);
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new = kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL);
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/* Inject TI if TVAL inverted */
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if (new > old)
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set_gcsr_estat(CPU_TIMER);
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}
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irq = (mask >> VIP_DELTA) & KVM_GINTC_IRQ_MASK;
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if (irq)
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set_csr_gintc(irq);
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}
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static void kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned long mask)
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{
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unsigned long irq;
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unsigned long old, new;
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irq = mask & KVM_ESTAT_INTI_MASK;
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if (irq) {
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old = kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL);
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clear_gcsr_estat(irq);
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new = kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL);
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/* Inject TI if TVAL inverted */
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if (new > old)
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set_gcsr_estat(CPU_TIMER);
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}
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irq = (mask >> VIP_DELTA) & KVM_GINTC_IRQ_MASK;
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if (irq)
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clear_csr_gintc(irq);
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}
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void kvm_deliver_intr(struct kvm_vcpu *vcpu)
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{
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unsigned long mask;
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mask = READ_ONCE(vcpu->arch.irq_clear);
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if (mask) {
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mask = xchg_relaxed(&vcpu->arch.irq_clear, 0);
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kvm_irq_clear(vcpu, mask);
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}
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mask = READ_ONCE(vcpu->arch.irq_pending);
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if (mask) {
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mask = xchg_relaxed(&vcpu->arch.irq_pending, 0);
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kvm_irq_deliver(vcpu, mask);
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}
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}
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int kvm_pending_timer(struct kvm_vcpu *vcpu)
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{
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return test_bit(INT_TI, &vcpu->arch.irq_pending);
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}
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/*
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* Only support illegal instruction or illegal Address Error exception,
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* Other exceptions are injected by hardware in kvm mode
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*/
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static void _kvm_deliver_exception(struct kvm_vcpu *vcpu,
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unsigned int code, unsigned int subcode)
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{
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unsigned long val, vec_size;
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/*
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* BADV is added for EXCCODE_ADE exception
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* Use PC register (GVA address) if it is instruction exeception
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* Else use BADV from host side (GPA address) for data exeception
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*/
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if (code == EXCCODE_ADE) {
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if (subcode == EXSUBCODE_ADEF)
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val = vcpu->arch.pc;
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else
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val = vcpu->arch.badv;
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kvm_write_hw_gcsr(LOONGARCH_CSR_BADV, val);
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}
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/* Set exception instruction */
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kvm_write_hw_gcsr(LOONGARCH_CSR_BADI, vcpu->arch.badi);
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/*
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* Save CRMD in PRMD
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* Set IRQ disabled and PLV0 with CRMD
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*/
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val = kvm_read_hw_gcsr(LOONGARCH_CSR_CRMD);
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kvm_write_hw_gcsr(LOONGARCH_CSR_PRMD, val);
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val = val & ~(CSR_CRMD_PLV | CSR_CRMD_IE);
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kvm_write_hw_gcsr(LOONGARCH_CSR_CRMD, val);
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/* Set exception PC address */
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kvm_write_hw_gcsr(LOONGARCH_CSR_ERA, vcpu->arch.pc);
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/*
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* Set exception code
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* Exception and interrupt can be inject at the same time
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* Hardware will handle exception first and then extern interrupt
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* Exception code is Ecode in ESTAT[16:21]
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* Interrupt code in ESTAT[0:12]
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*/
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val = kvm_read_hw_gcsr(LOONGARCH_CSR_ESTAT);
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val = (val & ~CSR_ESTAT_EXC) | code;
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kvm_write_hw_gcsr(LOONGARCH_CSR_ESTAT, val);
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/* Calculate expcetion entry address */
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val = kvm_read_hw_gcsr(LOONGARCH_CSR_ECFG);
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vec_size = (val & CSR_ECFG_VS) >> CSR_ECFG_VS_SHIFT;
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if (vec_size)
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vec_size = (1 << vec_size) * 4;
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val = kvm_read_hw_gcsr(LOONGARCH_CSR_EENTRY);
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vcpu->arch.pc = val + code * vec_size;
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}
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void kvm_deliver_exception(struct kvm_vcpu *vcpu)
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{
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unsigned int code;
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unsigned long *pending = &vcpu->arch.exception_pending;
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if (*pending) {
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code = __ffs(*pending);
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_kvm_deliver_exception(vcpu, code, vcpu->arch.esubcode);
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*pending = 0;
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vcpu->arch.esubcode = 0;
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}
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}
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