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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Greg UngererandGreg Ungerer
22371c4d8a
Convert all ColdFire specific timer setup code to only use the newly created internal register access methods. This is replacing the mixed and inconsistent use of readx/writex and __raw_readx/__raw_writex for internal SoC registers. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
83 lines
2.2 KiB
C
83 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* dma_timer.c -- Freescale ColdFire DMA Timer.
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*
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* Copyright (C) 2007, Benedikt Spranger <b.spranger@linutronix.de>
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* Copyright (C) 2008. Sebastian Siewior, Linutronix
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*
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*/
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#include <linux/clocksource.h>
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#include <linux/io.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfpit.h>
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#include <asm/mcfsim.h>
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#define DMA_TIMER_0 (0x00)
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#define DMA_TIMER_1 (0x40)
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#define DMA_TIMER_2 (0x80)
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#define DMA_TIMER_3 (0xc0)
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#define DTMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x400)
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#define DTXMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x402)
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#define DTER0 (MCF_IPSBAR + DMA_TIMER_0 + 0x403)
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#define DTRR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x404)
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#define DTCR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x408)
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#define DTCN0 (MCF_IPSBAR + DMA_TIMER_0 + 0x40c)
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#define DMA_FREQ ((MCF_CLK / 2) / 16)
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/* DTMR */
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#define DMA_DTMR_RESTART (1 << 3)
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#define DMA_DTMR_CLK_DIV_1 (1 << 1)
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#define DMA_DTMR_CLK_DIV_16 (2 << 1)
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#define DMA_DTMR_ENABLE (1 << 0)
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static u64 cf_dt_get_cycles(struct clocksource *cs)
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{
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return mcf_read32(DTCN0);
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}
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static struct clocksource clocksource_cf_dt = {
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.name = "coldfire_dma_timer",
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.rating = 200,
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.read = cf_dt_get_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init init_cf_dt_clocksource(void)
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{
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/*
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* We setup DMA timer 0 in free run mode. This incrementing counter is
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* used as a highly precious clock source. With MCF_CLOCK = 150 MHz we
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* get a ~213 ns resolution and the 32bit register will overflow almost
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* every 15 minutes.
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*/
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mcf_write8(0x00, DTXMR0);
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mcf_write8(0x00, DTER0);
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mcf_write32(0x00000000, DTRR0);
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mcf_write16(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
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return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ);
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}
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arch_initcall(init_cf_dt_clocksource);
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#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
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#define CYC2NS_SCALE ((1000000 << CYC2NS_SCALE_FACTOR) / (DMA_FREQ / 1000))
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static unsigned long long cycles2ns(unsigned long cycl)
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{
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return (unsigned long long) ((unsigned long long)cycl *
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CYC2NS_SCALE) >> CYC2NS_SCALE_FACTOR;
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}
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unsigned long long sched_clock(void)
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{
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unsigned long cycl = mcf_read32(DTCN0);
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return cycles2ns(cycl);
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}
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