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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Stafford Horne
aca063c902
The original commit8c30b0018f("openrisc: Add jump label support") copies from arm64 and does not properly consider how icache invalidation on remote cores works in OpenRISC. On OpenRISC remote icaches need to be invalidated otherwise static key's may remain state after updating. Fix SMP cache syncing by: 1. Properly invalidate remote core icaches on SMP systems by using icache_all_inv. The old code uses kick_all_cpus_sync() which runs a no-op IPI function call on remote CPU's which does execute a lot of code and flushes many cache lines in the process, but does not flush all and it's not correct on OpenRISC. 2. For architectures that do not have WRITETHROUGH caches be sure to flush the dcache after patching. To test this I first reproduced the issue using a custom test module [0]. The test confirmed that some icache lines maintained stale static_key code sequences after calling static_branch_enable(). After this patch there are no longer jump_label coherency issues. [0] https://github.com/stffrdhrn/or1k-utils/tree/master/tests/smp_static_key_test Cc: stable@vger.kernel.org # depends on openrisc: Add icache_all_inv Fixes:8c30b0018f("openrisc: Add jump label support") Signed-off-by: Stafford Horne <shorne@gmail.com>
52 lines
1.1 KiB
C
52 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2025 Chen Miao
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*
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* Based on arch/arm/kernel/jump_label.c
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*/
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#include <linux/jump_label.h>
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#include <linux/kernel.h>
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#include <linux/memory.h>
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#include <asm/bug.h>
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#include <asm/cacheflush.h>
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#include <asm/text-patching.h>
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bool arch_jump_label_transform_queue(struct jump_entry *entry,
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enum jump_label_type type)
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{
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void *addr = (void *)jump_entry_code(entry);
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u32 insn;
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if (type == JUMP_LABEL_JMP) {
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long offset;
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offset = jump_entry_target(entry) - jump_entry_code(entry);
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/*
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* The actual maximum range of the l.j instruction's offset is -134,217,728
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* ~ 134,217,724 (sign 26-bit imm).
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* For the original jump range, we need to right-shift N by 2 to obtain the
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* instruction's offset.
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*/
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WARN_ON_ONCE(offset < -134217728 || offset > 134217724);
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/* 26bit imm mask */
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offset = (offset >> 2) & 0x03ffffff;
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insn = offset;
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} else {
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insn = OPENRISC_INSN_NOP;
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}
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if (early_boot_irqs_disabled)
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copy_to_kernel_nofault(addr, &insn, sizeof(insn));
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else
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patch_insn_write(addr, insn);
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return true;
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}
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void arch_jump_label_transform_apply(void)
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{
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icache_all_inv();
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}
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