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Luca WeissandBjorn Andersson
bd09d87c55
On newer SoCs like Milos the CAMSS_TOP_GDSC power domains requires the enablement of the multimedia NoC, otherwise the GDSC will be stuck on 'off'. Add support for getting an interconnect path as specified in the SoC clock driver, and enabling/disabling that interconnect path when the GDSC is being enabled/disabled. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20260501-milos-camcc-icc-v2-3-bb83c1256cc3@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
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*/
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#ifndef __QCOM_GDSC_H__
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#define __QCOM_GDSC_H__
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#include <linux/err.h>
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#include <linux/pm_domain.h>
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struct icc_path;
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struct regmap;
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struct regulator;
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struct reset_controller_dev;
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/**
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* struct gdsc - Globally Distributed Switch Controller
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* @pd: generic power domain
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* @regmap: regmap for MMIO accesses
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* @gdscr: gsdc control register
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* @collapse_ctrl: APCS collapse-vote register
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* @collapse_mask: APCS collapse-vote mask
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* @gds_hw_ctrl: gds_hw_ctrl register
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* @cxcs: offsets of branch registers to toggle mem/periph bits in
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* @cxc_count: number of @cxcs
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* @pwrsts: Possible powerdomain power states
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* @en_rest_wait_val: transition delay value for receiving enr ack signal
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* @en_few_wait_val: transition delay value for receiving enf ack signal
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* @clk_dis_wait_val: transition delay value for halting clock
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* @resets: ids of resets associated with this gdsc
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* @reset_count: number of @resets
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* @rcdev: reset controller
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*/
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struct gdsc {
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struct generic_pm_domain pd;
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struct generic_pm_domain *parent;
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struct regmap *regmap;
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unsigned int gdscr;
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unsigned int collapse_ctrl;
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unsigned int collapse_mask;
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unsigned int gds_hw_ctrl;
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unsigned int clamp_io_ctrl;
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unsigned int *cxcs;
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unsigned int cxc_count;
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unsigned int en_rest_wait_val;
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unsigned int en_few_wait_val;
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unsigned int clk_dis_wait_val;
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const u8 pwrsts;
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/* Powerdomain allowable state bitfields */
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#define PWRSTS_OFF BIT(0)
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/*
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* There is no SW control to transition a GDSC into
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* PWRSTS_RET. This happens in HW when the parent
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* domain goes down to a low power state
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*/
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#define PWRSTS_RET BIT(1)
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#define PWRSTS_ON BIT(2)
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#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
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#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
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const u16 flags;
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#define VOTABLE BIT(0)
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#define CLAMP_IO BIT(1)
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#define HW_CTRL BIT(2)
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#define SW_RESET BIT(3)
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#define AON_RESET BIT(4)
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#define POLL_CFG_GDSCR BIT(5)
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#define ALWAYS_ON BIT(6)
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#define RETAIN_FF_ENABLE BIT(7)
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#define NO_RET_PERIPH BIT(8)
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#define HW_CTRL_TRIGGER BIT(9)
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struct reset_controller_dev *rcdev;
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unsigned int *resets;
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unsigned int reset_count;
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const char *supply;
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struct regulator *rsupply;
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bool needs_icc;
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unsigned int icc_path_index;
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struct icc_path *icc_path;
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};
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struct gdsc_desc {
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struct device *dev;
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struct gdsc **scs;
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size_t num;
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struct dev_pm_domain_list *pd_list;
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};
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#ifdef CONFIG_QCOM_GDSC
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int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
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struct regmap *);
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void gdsc_unregister(struct gdsc_desc *desc);
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int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain);
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#else
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static inline int gdsc_register(struct gdsc_desc *desc,
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struct reset_controller_dev *rcdev,
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struct regmap *r)
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{
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return -ENOSYS;
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}
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static inline void gdsc_unregister(struct gdsc_desc *desc) {};
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#endif /* CONFIG_QCOM_GDSC */
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#endif /* __QCOM_GDSC_H__ */
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