mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-08-09 06:14:34 +02:00
Jani Nikula
d1dc0c08e2
Add display specific helpers for getting the register offset, checking for equality and validity. Add them as static inlines for increased type safety. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/7fe12d4e5465778209ccf29359767a197b031dd9.1777972548.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
184 lines
4.8 KiB
C
184 lines
4.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DE_H__
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#define __INTEL_DE_H__
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#include "intel_display_core.h"
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#include "intel_dmc_wl.h"
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#include "intel_dsb.h"
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#include "intel_uncore.h"
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#include "intel_uncore_trace.h"
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static inline struct intel_uncore *__to_uncore(struct intel_display *display)
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{
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return to_intel_uncore(display->drm);
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}
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u8 intel_de_read8(struct intel_display *display, intel_reg_t reg);
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void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val);
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u16 intel_de_read16(struct intel_display *display, intel_reg_t reg);
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static inline u32
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intel_de_read(struct intel_display *display, intel_reg_t reg)
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{
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u32 val;
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intel_dmc_wl_get(display, reg);
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val = intel_uncore_read(__to_uncore(display), reg);
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intel_dmc_wl_put(display, reg);
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return val;
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}
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static inline u64
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intel_de_read64_2x32_volatile(struct intel_display *display,
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intel_reg_t lower_reg, intel_reg_t upper_reg)
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{
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u64 val;
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intel_dmc_wl_get(display, lower_reg);
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intel_dmc_wl_get(display, upper_reg);
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val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg,
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upper_reg);
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intel_dmc_wl_put(display, upper_reg);
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intel_dmc_wl_put(display, lower_reg);
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return val;
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}
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static inline u64
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intel_de_read64_2x32(struct intel_display *display, intel_reg_t reg)
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{
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intel_reg_t upper_reg = _MMIO(intel_reg_offset(reg) + 4);
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u32 lower, upper;
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lower = intel_de_read(display, reg);
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upper = intel_de_read(display, upper_reg);
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return (u64)upper << 32 | lower;
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}
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static inline void
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intel_de_posting_read(struct intel_display *display, intel_reg_t reg)
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{
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intel_dmc_wl_get(display, reg);
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intel_uncore_posting_read(__to_uncore(display), reg);
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intel_dmc_wl_put(display, reg);
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}
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static inline void
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intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val)
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{
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intel_dmc_wl_get(display, reg);
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intel_uncore_write(__to_uncore(display), reg, val);
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intel_dmc_wl_put(display, reg);
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}
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static inline u32
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intel_de_rmw(struct intel_display *display, intel_reg_t reg, u32 clear, u32 set)
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{
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u32 val;
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intel_dmc_wl_get(display, reg);
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val = intel_uncore_rmw(__to_uncore(display), reg, clear, set);
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intel_dmc_wl_put(display, reg);
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return val;
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}
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int intel_de_wait_us(struct intel_display *display, intel_reg_t reg,
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u32 mask, u32 value, unsigned int timeout_us,
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u32 *out_value);
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int intel_de_wait_ms(struct intel_display *display, intel_reg_t reg,
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u32 mask, u32 value, unsigned int timeout_ms,
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u32 *out_value);
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int intel_de_wait_fw_ms(struct intel_display *display, intel_reg_t reg,
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u32 mask, u32 value, unsigned int timeout_ms,
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u32 *out_value);
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int intel_de_wait_fw_us_atomic(struct intel_display *display, intel_reg_t reg,
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u32 mask, u32 value, unsigned int timeout_us,
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u32 *out_value);
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int intel_de_wait_for_set_us(struct intel_display *display, intel_reg_t reg,
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u32 mask, unsigned int timeout_us);
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int intel_de_wait_for_clear_us(struct intel_display *display, intel_reg_t reg,
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u32 mask, unsigned int timeout_us);
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int intel_de_wait_for_set_ms(struct intel_display *display, intel_reg_t reg,
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u32 mask, unsigned int timeout_ms);
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int intel_de_wait_for_clear_ms(struct intel_display *display, intel_reg_t reg,
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u32 mask, unsigned int timeout_ms);
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/*
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* Unlocked mmio-accessors, think carefully before using these.
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*
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* Certain architectures will die if the same cacheline is concurrently accessed
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* by different clients (e.g. on Ivybridge). Access to registers should
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* therefore generally be serialised, by either the dev_priv->uncore.lock or
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* a more localised lock guarding all access to that bank of registers.
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*/
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static inline u32
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intel_de_read_fw(struct intel_display *display, intel_reg_t reg)
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{
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u32 val;
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val = intel_uncore_read_fw(__to_uncore(display), reg);
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trace_i915_reg_rw(false, reg, val, sizeof(val), true);
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return val;
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}
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static inline void
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intel_de_write_fw(struct intel_display *display, intel_reg_t reg, u32 val)
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{
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trace_i915_reg_rw(true, reg, val, sizeof(val), true);
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intel_uncore_write_fw(__to_uncore(display), reg, val);
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}
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static inline u32
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intel_de_rmw_fw(struct intel_display *display, intel_reg_t reg, u32 clear, u32 set)
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{
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u32 old, val;
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old = intel_de_read_fw(display, reg);
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val = (old & ~clear) | set;
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intel_de_write_fw(display, reg, val);
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return old;
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}
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static inline u32
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intel_de_read_notrace(struct intel_display *display, intel_reg_t reg)
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{
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return intel_uncore_read_notrace(__to_uncore(display), reg);
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}
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static inline void
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intel_de_write_notrace(struct intel_display *display, intel_reg_t reg, u32 val)
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{
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intel_uncore_write_notrace(__to_uncore(display), reg, val);
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}
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static __always_inline void
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intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
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intel_reg_t reg, u32 val)
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{
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if (dsb)
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intel_dsb_reg_write(dsb, reg, val);
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else
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intel_de_write_fw(display, reg, val);
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}
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#endif /* __INTEL_DE_H__ */
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