mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-08-09 06:14:34 +02:00
Maxime RipardandDave Airlie
5164f7e7ff
The KMS framework uses two slightly different definitions for the state concept. For a given object (plane, CRTC, encoder, etc., so drm_$OBJECT_state), the state is the entire state of that object. However, at the device level, drm_atomic_state refers to a state update for a limited number of objects. Thus, drm_atomic_state isn't the entire device state, but only the full state of some objects in that device. This has been an endless source of confusion and thus bugs. We can rename the drm_atomic_state structure to drm_atomic_commit to make it less confusing. This patch was created using: rg -l drm_atomic_state | \ xargs sed -i 's/drm_atomic_state/drm_atomic_commit/g; s/drm_atomic_commit_helper/drm_atomic_state_helper/g' mv drivers/gpu/drm/tests/drm_atomic_state_test.c drivers/gpu/drm/tests/drm_atomic_commit_test.c Acked-by: Simona Vetter <simona.vetter@ffwll.ch> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patch.msgid.link/20260427-drm-drm-atomic-update-v4-1-c0e713bfdf25@kernel.org
99 lines
2.2 KiB
C
99 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef TEGRA_HUB_H
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#define TEGRA_HUB_H 1
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#include <drm/drm_plane.h>
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#include "plane.h"
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struct tegra_dc;
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struct tegra_windowgroup {
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unsigned int usecount;
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struct mutex lock;
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unsigned int index;
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struct host1x_client *parent;
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struct reset_control *rst;
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};
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struct tegra_shared_plane {
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struct tegra_plane base;
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struct tegra_windowgroup *wgrp;
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};
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static inline struct tegra_shared_plane *
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to_tegra_shared_plane(struct drm_plane *plane)
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{
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return container_of(plane, struct tegra_shared_plane, base.base);
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}
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struct tegra_display_hub_soc {
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unsigned int num_wgrps;
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bool supports_dsc;
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};
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struct tegra_display_hub {
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struct drm_private_obj base;
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struct host1x_client client;
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struct clk *clk_disp;
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struct clk *clk_dsc;
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struct clk *clk_hub;
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struct reset_control *rst;
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unsigned int num_heads;
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struct clk **clk_heads;
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const struct tegra_display_hub_soc *soc;
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struct tegra_windowgroup *wgrps;
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};
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static inline struct tegra_display_hub *
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to_tegra_display_hub(struct host1x_client *client)
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{
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return container_of(client, struct tegra_display_hub, client);
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}
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struct tegra_display_hub_state {
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struct drm_private_state base;
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struct tegra_dc *dc;
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unsigned long rate;
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struct clk *clk;
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};
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static inline struct tegra_display_hub_state *
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to_tegra_display_hub_state(struct drm_private_state *priv)
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{
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return container_of(priv, struct tegra_display_hub_state, base);
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}
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struct tegra_plane;
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int tegra_display_hub_prepare(struct tegra_display_hub *hub);
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void tegra_display_hub_cleanup(struct tegra_display_hub *hub);
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struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
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struct tegra_dc *dc,
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unsigned int wgrp,
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unsigned int index,
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enum drm_plane_type type);
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int tegra_display_hub_atomic_check(struct drm_device *drm,
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struct drm_atomic_commit *state);
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void tegra_display_hub_atomic_commit(struct drm_device *drm,
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struct drm_atomic_commit *state);
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#define DC_CMD_IHUB_COMMON_MISC_CTL 0x068
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#define LATENCY_EVENT (1 << 3)
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#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER 0x451
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#define CURS_SLOTS(x) (((x) & 0xff) << 8)
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#define WGRP_SLOTS(x) (((x) & 0xff) << 0)
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#endif /* TEGRA_HUB_H */
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