mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-08-09 06:14:34 +02:00
Gary GuoandDanilo Krummrich
99676aed1f
Currently Nova code uses `&'a Bar0` a lot. This is `&'a Mmio`, where `Mmio` represents an owned MMIO region; this type only exists as a target for `Deref` so `Bar` and `IoMem` can share code and should be avoided to be named directly. The upcoming I/O projection series would make `Io` trait much simpler to implement, and thus the owned MMIO type would be removed in favour of direct `Io` implementation on `Bar` and `IoMem`. Add lifetime parameter to `Bar0<'a>` and change it to be alias of `&'a pci::Bar<'a, ..>`. This also prepares Nova core so that when I/O projection series land, this could be changed to using a MMIO view type directly which avoids double indirection. Signed-off-by: Gary Guo <gary@garyguo.net> Acked-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260602170416.2268531-1-gary@kernel.org [ Rebase onto latest drm-rust-next (Blackwell enablement). - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
80 lines
2.2 KiB
Rust
80 lines
2.2 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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use kernel::{
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io::{
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poll::read_poll_timeout,
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register::{
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RegisterBase,
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WithBase, //
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},
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Io,
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},
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prelude::*,
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time::Delta, //
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};
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use crate::{
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driver::Bar0,
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falcon::{
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Falcon,
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FalconEngine,
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PFalcon2Base,
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PFalconBase, //
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},
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regs,
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};
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/// Pattern returned by GSP register reads while the PRIV target mask still blocks CPU access.
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const GSP_TARGET_MASK_LOCKED_PATTERN: u32 = 0xbadf_4100;
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const GSP_TARGET_MASK_LOCKED_MASK: u32 = 0xffff_ff00;
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/// Type specifying the `Gsp` falcon engine. Cannot be instantiated.
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pub(crate) struct Gsp(());
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impl RegisterBase<PFalconBase> for Gsp {
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const BASE: usize = 0x00110000;
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}
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impl RegisterBase<PFalcon2Base> for Gsp {
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const BASE: usize = 0x00111000;
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}
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impl FalconEngine for Gsp {}
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impl Falcon<Gsp> {
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/// Clears the SWGEN0 bit in the Falcon's IRQ status clear register to
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/// allow GSP to signal CPU for processing new messages in message queue.
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pub(crate) fn clear_swgen0_intr(&self, bar: Bar0<'_>) {
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bar.write(
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WithBase::of::<Gsp>(),
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regs::NV_PFALCON_FALCON_IRQSCLR::zeroed().with_swgen0(true),
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);
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}
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/// Checks if GSP reload/resume has completed during the boot process.
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pub(crate) fn check_reload_completed(&self, bar: Bar0<'_>, timeout: Delta) -> Result<bool> {
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read_poll_timeout(
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|| Ok(bar.read(regs::NV_PGC6_BSI_SECURE_SCRATCH_14)),
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|val| val.boot_stage_3_handoff(),
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Delta::ZERO,
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timeout,
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)
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.map(|_| true)
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}
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/// Returns whether the RISC-V branch privilege lockdown bit is set.
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pub(crate) fn riscv_branch_privilege_lockdown(&self, bar: Bar0<'_>) -> bool {
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bar.read(regs::NV_PFALCON_FALCON_HWCFG2::of::<Gsp>())
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.riscv_br_priv_lockdown()
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}
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/// Returns whether GSP registers can be read by the CPU.
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pub(crate) fn priv_target_mask_released(&self, bar: Bar0<'_>) -> bool {
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let hwcfg2 = bar
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.read(regs::NV_PFALCON_FALCON_HWCFG2::of::<Gsp>())
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.into_raw();
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hwcfg2 != 0 && (hwcfg2 & GSP_TARGET_MASK_LOCKED_MASK) != GSP_TARGET_MASK_LOCKED_PATTERN
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}
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}
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