mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-08-09 06:14:34 +02:00
Gary GuoandDanilo Krummrich
99676aed1f
Currently Nova code uses `&'a Bar0` a lot. This is `&'a Mmio`, where `Mmio` represents an owned MMIO region; this type only exists as a target for `Deref` so `Bar` and `IoMem` can share code and should be avoided to be named directly. The upcoming I/O projection series would make `Io` trait much simpler to implement, and thus the owned MMIO type would be removed in favour of direct `Io` implementation on `Bar` and `IoMem`. Add lifetime parameter to `Bar0<'a>` and change it to be alias of `&'a pci::Bar<'a, ..>`. This also prepares Nova core so that when I/O projection series land, this could be changed to using a MMIO view type directly which avoids double indirection. Signed-off-by: Gary Guo <gary@garyguo.net> Acked-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260602170416.2268531-1-gary@kernel.org [ Rebase onto latest drm-rust-next (Blackwell enablement). - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
57 lines
1.7 KiB
Rust
57 lines
1.7 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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use kernel::prelude::*;
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use crate::{
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driver::Bar0,
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gpu::{
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Architecture,
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Chipset, //
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},
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};
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mod ga100;
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mod ga102;
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mod gb100;
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mod gb202;
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mod gh100;
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mod tu102;
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pub(crate) trait FbHal {
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/// Returns the address of the currently-registered sysmem flush page.
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fn read_sysmem_flush_page(&self, bar: Bar0<'_>) -> u64;
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/// Register `addr` as the address of the sysmem flush page.
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///
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/// This might fail if the address is too large for the receiving register.
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fn write_sysmem_flush_page(&self, bar: Bar0<'_>, addr: u64) -> Result;
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/// Returns `true` is display is supported.
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fn supports_display(&self, bar: Bar0<'_>) -> bool;
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/// Returns the VRAM size, in bytes.
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fn vidmem_size(&self, bar: Bar0<'_>) -> u64;
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/// Returns the amount of VRAM to reserve for the PMU.
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fn pmu_reserved_size(&self) -> u32;
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/// Returns the non-WPR heap size for this chipset, in bytes.
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fn non_wpr_heap_size(&self) -> u32;
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/// Returns the FRTS size, in bytes.
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fn frts_size(&self) -> u64;
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}
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/// Returns the HAL corresponding to `chipset`.
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pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn FbHal {
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match chipset.arch() {
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Architecture::Turing => tu102::TU102_HAL,
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Architecture::Ampere if chipset == Chipset::GA100 => ga100::GA100_HAL,
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Architecture::Ampere | Architecture::Ada => ga102::GA102_HAL,
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Architecture::Hopper => gh100::GH100_HAL,
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Architecture::BlackwellGB10x => gb100::GB100_HAL,
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Architecture::BlackwellGB20x => gb202::GB202_HAL,
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}
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}
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