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Bjorn Helgaas
dd81c6524b
- Add pci_host_common_link_train_delay() for the mandatory delay after > 5GT/s Link training completes and use it for cadence HPA, j721e, LGA; dwc; aardvark, mediatek-gen3, rzg3s (Hans Zhang) * pci/controller/link_train_delay: PCI: rzg3s-host: Use common pci_host_common_link_train_delay() helper PCI: mediatek-gen3: Add 100 ms delay after link up PCI: aardvark: Add 100 ms delay after link training PCI: dwc: Use common pci_host_common_link_train_delay() helper PCI: cadence-hpa: Add post-link delay PCI: cadence: Add post-link delay for LGA and j721e glue driver PCI: Add pci_host_common_link_train_delay() helper # Conflicts: # drivers/pci/controller/pci-host-common.h
72 lines
1.9 KiB
C
72 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Common library for PCI host controller drivers
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*
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* Copyright (C) 2014 ARM Limited
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*/
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#ifndef _PCI_HOST_COMMON_H
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#define _PCI_HOST_COMMON_H
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#include <linux/delay.h>
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#include "../pci.h"
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struct pci_ecam_ops;
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/**
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* struct pci_host_perst - PERST# GPIO descriptor
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* @list: List node for linking multiple PERST# GPIOs
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* @desc: GPIO descriptor for PERST# signal
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*
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* This structure holds a single PERST# GPIO descriptor.
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*/
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struct pci_host_perst {
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struct list_head list;
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struct gpio_desc *desc;
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};
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/**
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* struct pci_host_port - Generic Root Port properties
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* @list: List node for linking multiple ports
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* @perst: List of PERST# GPIO descriptors for this port and its children
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*
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* This structure contains common properties that can be parsed from
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* Root Port device tree nodes.
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*/
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struct pci_host_port {
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struct list_head list;
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struct list_head perst;
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};
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void pci_host_common_delete_ports(void *data);
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int pci_host_common_parse_ports(struct device *dev,
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struct pci_host_bridge *bridge);
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int pci_host_common_probe(struct platform_device *pdev);
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int pci_host_common_init(struct platform_device *pdev,
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struct pci_host_bridge *bridge,
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const struct pci_ecam_ops *ops);
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void pci_host_common_remove(struct platform_device *pdev);
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struct pci_config_window *pci_host_common_ecam_create(struct device *dev,
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struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops);
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bool pci_host_common_d3cold_possible(struct pci_host_bridge *bridge,
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bool *pme_capable);
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/**
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* pci_host_common_link_train_delay - Wait 100 ms if link speed > 5 GT/s
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* @max_link_speed: the maximum link speed (2 = 5.0 GT/s, 3 = 8.0 GT/s, ...)
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*
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* Must be called after Link training completes and before the first
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* Configuration Request is sent.
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*/
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static inline void pci_host_common_link_train_delay(int max_link_speed)
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{
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if (max_link_speed > 2)
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msleep(PCIE_RESET_CONFIG_WAIT_MS);
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}
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#endif
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