mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-08-09 06:14:34 +02:00
Linus Torvalds
31b43c079f
Pull SoC driver updates from Arnd Bergmann:
"The driver updates again are all over the place with many minor fixes
going into platform specific code. The most notable changes are:
- Support for Microchip pic64gx system controllers
- Work on cleaning up devicetree bindings for SoC drivers, and
converting them into the new format
- Lots of smaller changes for Qualcomm SoC drivers, including support
for a number of newly supported chips
- reset controller API cleanups and a new driver for Cix Sky1
- Reworks of the Tegra PMC and CBB drivers, along with a change to
how individual Tegra SoCs get selected in Kconfig and BPMP firmware
driver updates including a refresh of the ABI header to match the
version used by firmware
- STM32 updates to the firewall bus driver and support for the debug
bus through OP-TEE
- SCMI firmware driver improvements for reliability, in particular
for dealing with broken firmware interrupts
- Memory driver updates for Tegra, and a patch to remove the unused
Baikal T1 driver"
* tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits)
firmware: arm_ffa: Use the correct buffer size during RXTX_MAP
firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X
clk: spear: fix resource leak in clk_register_vco_pll()
reset: rzv2h-usb2phy: Add support for VBUS mux controller registration
reset: rzv2h-usb2phy: Convert to regmap API
dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset
dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property
soc: microchip: add mpfs gpio interrupt mux driver
dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux
gpio: mpfs: Add interrupt support
soc: qcom: ubwc: add helpers to get programmable values
soc: qcom: ubwc: add helper to get min_acc length
firmware: qcom: scm: Register gunyah watchdog device
soc: qcom: socinfo: Add SoC ID for SA8650P
dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P
firmware: qcom: scm: Allow QSEECOM on Mahua CRD
soc: qcom: wcnss: simplify allocation of req
soc: qcom: pd-mapper: Add support for Eliza
soc: qcom: aoss: compare against normalized cooling state
soc: qcom: llcc: fix v1 SB syndrome register offset
...
104 lines
2.8 KiB
C
104 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __QCOM_PDR_HELPER_INTERNAL__
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#define __QCOM_PDR_HELPER_INTERNAL__
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#include <linux/soc/qcom/pdr.h>
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#define SERVREG_REGISTER_LISTENER_REQ 0x20
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#define SERVREG_GET_DOMAIN_LIST_REQ 0x21
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#define SERVREG_STATE_UPDATED_IND_ID 0x22
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#define SERVREG_SET_ACK_REQ 0x23
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#define SERVREG_RESTART_PD_REQ 0x24
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#define SERVREG_LOC_PFR_REQ 0x24
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#define SERVREG_DOMAIN_LIST_LENGTH 32
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#define SERVREG_RESTART_PD_REQ_MAX_LEN 67
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#define SERVREG_REGISTER_LISTENER_REQ_LEN 71
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#define SERVREG_SET_ACK_REQ_LEN 72
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#define SERVREG_GET_DOMAIN_LIST_REQ_MAX_LEN 74
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#define SERVREG_STATE_UPDATED_IND_MAX_LEN 79
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#define SERVREG_GET_DOMAIN_LIST_RESP_MAX_LEN 2389
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#define SERVREG_LOC_PFR_RESP_MAX_LEN 10
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struct servreg_location_entry {
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char name[SERVREG_NAME_LENGTH + 1];
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u8 service_data_valid;
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u32 service_data;
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u32 instance;
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};
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struct servreg_get_domain_list_req {
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char service_name[SERVREG_NAME_LENGTH + 1];
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u8 domain_offset_valid;
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u32 domain_offset;
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};
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struct servreg_get_domain_list_resp {
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struct qmi_response_type_v01 resp;
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u8 total_domains_valid;
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u16 total_domains;
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u8 db_rev_count_valid;
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u16 db_rev_count;
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u8 domain_list_valid;
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u32 domain_list_len;
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struct servreg_location_entry domain_list[SERVREG_DOMAIN_LIST_LENGTH];
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};
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struct servreg_register_listener_req {
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u8 enable;
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char service_path[SERVREG_NAME_LENGTH + 1];
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};
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struct servreg_register_listener_resp {
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struct qmi_response_type_v01 resp;
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u8 curr_state_valid;
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enum servreg_service_state curr_state;
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};
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struct servreg_restart_pd_req {
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char service_path[SERVREG_NAME_LENGTH + 1];
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};
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struct servreg_restart_pd_resp {
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struct qmi_response_type_v01 resp;
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};
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struct servreg_state_updated_ind {
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enum servreg_service_state curr_state;
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char service_path[SERVREG_NAME_LENGTH + 1];
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u16 transaction_id;
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};
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struct servreg_set_ack_req {
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char service_path[SERVREG_NAME_LENGTH + 1];
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u16 transaction_id;
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};
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struct servreg_set_ack_resp {
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struct qmi_response_type_v01 resp;
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};
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struct servreg_loc_pfr_req {
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char service[SERVREG_NAME_LENGTH + 1];
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char reason[SERVREG_PFR_LENGTH + 1];
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};
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struct servreg_loc_pfr_resp {
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struct qmi_response_type_v01 rsp;
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};
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extern const struct qmi_elem_info servreg_get_domain_list_req_ei[];
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extern const struct qmi_elem_info servreg_get_domain_list_resp_ei[];
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extern const struct qmi_elem_info servreg_register_listener_req_ei[];
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extern const struct qmi_elem_info servreg_register_listener_resp_ei[];
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extern const struct qmi_elem_info servreg_restart_pd_req_ei[];
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extern const struct qmi_elem_info servreg_restart_pd_resp_ei[];
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extern const struct qmi_elem_info servreg_state_updated_ind_ei[];
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extern const struct qmi_elem_info servreg_set_ack_req_ei[];
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extern const struct qmi_elem_info servreg_set_ack_resp_ei[];
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extern const struct qmi_elem_info servreg_loc_pfr_req_ei[];
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extern const struct qmi_elem_info servreg_loc_pfr_resp_ei[];
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#endif
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