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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-08-09 06:14:34 +02:00
Konrad DybcioandMika Westerberg
e241d98e04
Add a new file encapsulating most of the PCI NHI specifics (intentionally leaving some odd cookies behind to make the layering simpler). Most notably, separate out nhi_probe() to make it easier to register other types of NHIs. Also, fold in Intel Icelake (nhi_ops.c) support to contain all PCIe-related bits in pci.c. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
133 lines
5.0 KiB
C
133 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Thunderbolt driver - NHI driver
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*
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* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
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* Copyright (C) 2018, Intel Corporation
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*/
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#ifndef DSL3510_H_
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#define DSL3510_H_
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#include <linux/thunderbolt.h>
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enum nhi_fw_mode {
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NHI_FW_SAFE_MODE,
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NHI_FW_AUTH_MODE,
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NHI_FW_EP_MODE,
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NHI_FW_CM_MODE,
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};
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enum nhi_mailbox_cmd {
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NHI_MAILBOX_SAVE_DEVS = 0x05,
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NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06,
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NHI_MAILBOX_DRV_UNLOADS = 0x07,
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NHI_MAILBOX_DISCONNECT_PA = 0x10,
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NHI_MAILBOX_DISCONNECT_PB = 0x11,
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NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
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};
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int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
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enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);
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void nhi_enable_int_throttling(struct tb_nhi *nhi);
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void nhi_disable_interrupts(struct tb_nhi *nhi);
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void nhi_interrupt_work(struct work_struct *work);
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irqreturn_t nhi_msi(int irq, void *data);
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irqreturn_t ring_msix(int irq, void *data);
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int nhi_probe(struct tb_nhi *nhi);
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void nhi_shutdown(struct tb_nhi *nhi);
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extern const struct dev_pm_ops nhi_pm_ops;
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/**
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* struct tb_nhi_ops - NHI specific optional operations
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* @init: NHI specific initialization
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* @suspend_noirq: NHI specific suspend_noirq hook
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* @resume_noirq: NHI specific resume_noirq hook
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* @runtime_suspend: NHI specific runtime_suspend hook
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* @runtime_resume: NHI specific runtime_resume hook
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* @shutdown: NHI specific shutdown
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* @pre_nvm_auth: hook to run before Thunderbolt 3 NVM authentication
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* @post_nvm_auth: hook to run after Thunderbolt 3 NVM authentication
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* @request_ring_irq: NHI specific interrupt retrieval hook
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* @release_ring_irq: NHI specific interrupt release hook
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* @is_present: Whether the device is currently present on the parent bus
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* @init_interrupts: NHI specific interrupt initialization hook
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*/
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struct tb_nhi_ops {
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int (*init)(struct tb_nhi *nhi);
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int (*suspend_noirq)(struct tb_nhi *nhi, bool wakeup);
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int (*resume_noirq)(struct tb_nhi *nhi);
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int (*runtime_suspend)(struct tb_nhi *nhi);
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int (*runtime_resume)(struct tb_nhi *nhi);
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void (*shutdown)(struct tb_nhi *nhi);
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void (*pre_nvm_auth)(struct tb_nhi *nhi);
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void (*post_nvm_auth)(struct tb_nhi *nhi);
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int (*request_ring_irq)(struct tb_ring *ring, bool no_suspend);
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void (*release_ring_irq)(struct tb_ring *ring);
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bool (*is_present)(struct tb_nhi *nhi);
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int (*init_interrupts)(struct tb_nhi *nhi);
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};
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/*
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* PCI IDs used in this driver from Win Ridge forward. There is no
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* need for the PCI quirk anymore as we will use ICM also on Apple
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* hardware.
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*/
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#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_2C_NHI 0x1134
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#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_4C_NHI 0x1137
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#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d
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#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e7
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e8
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef
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#define PCI_DEVICE_ID_INTEL_ADL_NHI0 0x463e
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#define PCI_DEVICE_ID_INTEL_ADL_NHI1 0x466d
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#define PCI_DEVICE_ID_INTEL_WCL_NHI0 0x4d33
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#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI 0x5781
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#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI 0x5784
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#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_80G_BRIDGE 0x5786
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#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_40G_BRIDGE 0x57a4
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#define PCI_DEVICE_ID_INTEL_MTL_M_NHI0 0x7eb2
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#define PCI_DEVICE_ID_INTEL_MTL_P_NHI0 0x7ec2
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#define PCI_DEVICE_ID_INTEL_MTL_P_NHI1 0x7ec3
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#define PCI_DEVICE_ID_INTEL_ICL_NHI1 0x8a0d
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#define PCI_DEVICE_ID_INTEL_ICL_NHI0 0x8a17
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#define PCI_DEVICE_ID_INTEL_TGL_NHI0 0x9a1b
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#define PCI_DEVICE_ID_INTEL_TGL_NHI1 0x9a1d
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#define PCI_DEVICE_ID_INTEL_TGL_H_NHI0 0x9a1f
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#define PCI_DEVICE_ID_INTEL_TGL_H_NHI1 0x9a21
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#define PCI_DEVICE_ID_INTEL_RPL_NHI0 0xa73e
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#define PCI_DEVICE_ID_INTEL_RPL_NHI1 0xa76d
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#define PCI_DEVICE_ID_INTEL_LNL_NHI0 0xa833
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#define PCI_DEVICE_ID_INTEL_LNL_NHI1 0xa834
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#define PCI_DEVICE_ID_INTEL_PTL_M_NHI0 0xe333
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#define PCI_DEVICE_ID_INTEL_PTL_M_NHI1 0xe334
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#define PCI_DEVICE_ID_INTEL_PTL_P_NHI0 0xe433
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#define PCI_DEVICE_ID_INTEL_PTL_P_NHI1 0xe434
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#define PCI_CLASS_SERIAL_USB_USB4 0x0c0340
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/* Host interface quirks */
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#define QUIRK_AUTO_CLEAR_INT BIT(0)
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#define QUIRK_E2E BIT(1)
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/*
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* Minimal number of vectors when we use MSI-X. Two for control channel
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* Rx/Tx and the rest four are for cross domain DMA paths.
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*/
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#define MSIX_MIN_VECS 6
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#define MSIX_MAX_VECS 16
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#endif
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