mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-08-09 06:14:34 +02:00
Li RongQingandHelge Deller
5dbe5b65df
The big_swap(p) macro was intended to swap bytes within 16-bit halves
of a 32-bit value. However, because the bitwise shift operators (<<, >>)
have higher precedence than the bitwise AND operator (&), the original
code failed to perform any shifting on the masked bits.
For example, 'p & 0xff00ff00 >> 8' was evaluated as 'p &
(0xff00ff00 >> 8)', effectively neutralizing the intended swap.
Fix this by adding parentheses to ensure the bitwise AND is performed
before the shift, correctly implementing the byte swap logic.
Fixes: 1461d66728 ("staging: sm7xxfb: merge sm712fb with fbdev")
Cc: stable@vger.kernel.org
Signed-off-by: Li RongQing <lirongqing@baidu.com>
Signed-off-by: Helge Deller <deller@gmx.de>
113 lines
3.0 KiB
C
113 lines
3.0 KiB
C
/*
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* Silicon Motion SM712 frame buffer device
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*
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* Copyright (C) 2006 Silicon Motion Technology Corp.
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* Authors: Ge Wang, gewang@siliconmotion.com
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* Boyod boyod.yang@siliconmotion.com.cn
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*
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* Copyright (C) 2009 Lemote, Inc.
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* Author: Wu Zhangjin, wuzhangjin@gmail.com
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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#define FB_ACCEL_SMI_LYNX 88
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#define SCREEN_X_RES 1024
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#define SCREEN_Y_RES_PC 768
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#define SCREEN_Y_RES_NETBOOK 600
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#define SCREEN_BPP 16
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#define dac_reg (0x3c8)
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#define dac_val (0x3c9)
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extern void __iomem *smtc_regbaseaddress;
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#define smtc_mmiowb(dat, reg) writeb(dat, smtc_regbaseaddress + reg)
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#define smtc_mmiorb(reg) readb(smtc_regbaseaddress + reg)
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#define SIZE_SR00_SR04 (0x04 - 0x00 + 1)
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#define SIZE_SR10_SR24 (0x24 - 0x10 + 1)
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#define SIZE_SR30_SR75 (0x75 - 0x30 + 1)
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#define SIZE_SR80_SR93 (0x93 - 0x80 + 1)
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#define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1)
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#define SIZE_GR00_GR08 (0x08 - 0x00 + 1)
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#define SIZE_AR00_AR14 (0x14 - 0x00 + 1)
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#define SIZE_CR00_CR18 (0x18 - 0x00 + 1)
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#define SIZE_CR30_CR4D (0x4D - 0x30 + 1)
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#define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1)
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static inline void smtc_crtcw(int reg, int val)
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{
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smtc_mmiowb(reg, 0x3d4);
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smtc_mmiowb(val, 0x3d5);
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}
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static inline void smtc_grphw(int reg, int val)
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{
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smtc_mmiowb(reg, 0x3ce);
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smtc_mmiowb(val, 0x3cf);
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}
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static inline void smtc_attrw(int reg, int val)
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{
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smtc_mmiorb(0x3da);
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smtc_mmiowb(reg, 0x3c0);
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smtc_mmiorb(0x3c1);
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smtc_mmiowb(val, 0x3c0);
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}
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static inline void smtc_seqw(int reg, int val)
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{
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smtc_mmiowb(reg, 0x3c4);
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smtc_mmiowb(val, 0x3c5);
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}
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static inline unsigned int smtc_seqr(int reg)
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{
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smtc_mmiowb(reg, 0x3c4);
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return smtc_mmiorb(0x3c5);
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}
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/* The next structure holds all information relevant for a specific video mode.
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*/
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struct modeinit {
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int mmsizex;
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int mmsizey;
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int bpp;
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int hz;
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unsigned char init_misc;
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unsigned char init_sr00_sr04[SIZE_SR00_SR04];
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unsigned char init_sr10_sr24[SIZE_SR10_SR24];
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unsigned char init_sr30_sr75[SIZE_SR30_SR75];
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unsigned char init_sr80_sr93[SIZE_SR80_SR93];
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unsigned char init_sra0_sraf[SIZE_SRA0_SRAF];
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unsigned char init_gr00_gr08[SIZE_GR00_GR08];
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unsigned char init_ar00_ar14[SIZE_AR00_AR14];
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unsigned char init_cr00_cr18[SIZE_CR00_CR18];
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unsigned char init_cr30_cr4d[SIZE_CR30_CR4D];
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unsigned char init_cr90_cra7[SIZE_CR90_CRA7];
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};
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#ifdef __BIG_ENDIAN
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#define pal_rgb(r, g, b, val) (((r & 0xf800) >> 8) | \
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((g & 0xe000) >> 13) | \
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((g & 0x1c00) << 3) | \
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((b & 0xf800) >> 3))
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#define big_addr 0x800000
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#define mmio_addr 0x00800000
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#define seqw17() smtc_seqw(0x17, 0x30)
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#define big_pixel_depth(p, d) {if (p == 24) {p = 32; d = 32; } }
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#define big_swap(p) (((p & 0xff00ff00) >> 8) | ((p & 0x00ff00ff) << 8))
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#else
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#define pal_rgb(r, g, b, val) val
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#define big_addr 0
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#define mmio_addr 0x00c00000
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#define seqw17() do { } while (0)
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#define big_pixel_depth(p, d) do { } while (0)
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#define big_swap(p) p
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#endif
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