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Cássio GabrielandTakashi Iwai
e76296d137
The PCXHR and HR222 clock paths duplicate the PLL divider calculation and register encoding. The HR222 variant extends the same format with an additional range for rates above those supported by the older boards. Move the complete encoding into pcxhr_pll_freq_register() and pass each hardware path its existing maximum frequency. The additional encoding branch is unreachable with the older 110 kHz limit, so this preserves both paths' accepted ranges and generated register values while removing the duplicate implementation and its long-standing TODO. Signed-off-by: Cássio Gabriel <cassiogabrielcontato@gmail.com> Link: https://patch.msgid.link/20260612-alsa-pcxhr-pll-helper-v1-1-c84ae2bd2e9b@gmail.com Signed-off-by: Takashi Iwai <tiwai@suse.de>