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Chen PeiandArnaldo Carvalho de Melo
6a082433bc
Implement __perf_sdt_arg_parse_op_riscv() to convert RISC-V GCC-generated SDT probe operands into uprobe-compatible format, and register it in the perf_sdt_arg_parse_op() dispatcher for EM_RISCV. RISC-V GCC uses the 'nor' constraint for SDT arguments, producing operands in the following formats: Format Example Uprobe format ----------- ----------- ------------- register a0 %a0 memory (+) 8(a0) +8(%a0) memory (-) -20(s0) -20(%s0) constant 99 (skip, not supported by uprobe) Key differences from other architectures: - Register names use ABI aliases (a0-a7, t0-t6, s0-s11, sp, ra, etc.) without any '%' prefix, unlike x86 (%rax) or arm64 (x0). - Memory operands use OFFSET(REG) syntax where OFFSET may be negative, unlike arm64's [sp, NUM] or powerpc's NUM(%rREG). Two regexes are used: - SDT_OP_REGEX1: matches RISC-V ABI register names saved in pt_regs - SDT_OP_REGEX2: matches [-]NUM(REG) memory operands Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Chen Pei <cp0613@linux.alibaba.com> Cc: Alexandre Ghiti <alex@ghiti.fr> Cc: Dapeng Mi <dapeng1.mi@linux.intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Paul Walmsley <pjw@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
80 lines
2.5 KiB
C
80 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __PERF_REGS_H
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#define __PERF_REGS_H
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#include <linux/types.h>
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#include <linux/compiler.h>
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struct regs_dump;
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enum {
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SDT_ARG_VALID = 0,
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SDT_ARG_SKIP,
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};
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int perf_sdt_arg_parse_op(uint16_t e_machine, char *old_op, char **new_op);
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uint64_t perf_intr_reg_mask(uint16_t e_machine);
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uint64_t perf_user_reg_mask(uint16_t e_machine);
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const char *perf_reg_name(int id, uint16_t e_machine, uint32_t e_flags);
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int perf_reg_value(u64 *valp, struct regs_dump *regs, int id);
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uint64_t perf_arch_reg_ip(uint16_t e_machine);
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uint64_t perf_arch_reg_sp(uint16_t e_machine);
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int __perf_sdt_arg_parse_op_arm64(char *old_op, char **new_op);
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uint64_t __perf_reg_mask_arm64(bool intr);
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const char *__perf_reg_name_arm64(int id);
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uint64_t __perf_reg_ip_arm64(void);
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uint64_t __perf_reg_sp_arm64(void);
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uint64_t __perf_reg_mask_arm(bool intr);
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const char *__perf_reg_name_arm(int id);
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uint64_t __perf_reg_ip_arm(void);
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uint64_t __perf_reg_sp_arm(void);
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uint64_t __perf_reg_mask_csky(bool intr);
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const char *__perf_reg_name_csky(int id, uint32_t e_flags);
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uint64_t __perf_reg_ip_csky(void);
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uint64_t __perf_reg_sp_csky(void);
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uint64_t __perf_reg_mask_loongarch(bool intr);
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const char *__perf_reg_name_loongarch(int id);
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uint64_t __perf_reg_ip_loongarch(void);
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uint64_t __perf_reg_sp_loongarch(void);
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uint64_t __perf_reg_mask_mips(bool intr);
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const char *__perf_reg_name_mips(int id);
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uint64_t __perf_reg_ip_mips(void);
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uint64_t __perf_reg_sp_mips(void);
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int __perf_sdt_arg_parse_op_powerpc(char *old_op, char **new_op);
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uint64_t __perf_reg_mask_powerpc(bool intr);
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const char *__perf_reg_name_powerpc(int id);
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uint64_t __perf_reg_ip_powerpc(void);
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uint64_t __perf_reg_sp_powerpc(void);
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int __perf_sdt_arg_parse_op_riscv(char *old_op, char **new_op);
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uint64_t __perf_reg_mask_riscv(bool intr);
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const char *__perf_reg_name_riscv(int id);
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uint64_t __perf_reg_ip_riscv(void);
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uint64_t __perf_reg_sp_riscv(void);
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uint64_t __perf_reg_mask_s390(bool intr);
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const char *__perf_reg_name_s390(int id);
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uint64_t __perf_reg_ip_s390(void);
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uint64_t __perf_reg_sp_s390(void);
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int __perf_sdt_arg_parse_op_s390(char *old_op, char **new_op);
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int __perf_sdt_arg_parse_op_x86(char *old_op, char **new_op);
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uint64_t __perf_reg_mask_x86(bool intr);
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const char *__perf_reg_name_x86(int id);
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uint64_t __perf_reg_ip_x86(void);
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uint64_t __perf_reg_sp_x86(void);
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static inline uint64_t DWARF_MINIMAL_REGS(uint16_t e_machine)
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{
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return (1ULL << perf_arch_reg_ip(e_machine)) | (1ULL << perf_arch_reg_sp(e_machine));
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}
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#endif /* __PERF_REGS_H */
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