mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-08-09 06:14:34 +02:00
David MatlackandSean Christopherson
26f8453288
Use u64 instead of uint64_t to make the KVM selftests code more concise and more similar to the kernel (since selftests are primarily developed by kernel developers). This commit was generated with the following command: git ls-files tools/testing/selftests/kvm | xargs sed -i 's/uint64_t/u64/g' Then by manually adjusting whitespace to make checkpatch.pl happy. Include <linux/types.h> in include/kvm_util_types.h, iinclude/test_util.h, and include/x86/pmu.h to pick up the tools-defined u64. Arguably, all headers (especially kvm_util_types.h) should have already been including stdint.h to get uint64_t from the libc headers, but the missing dependency only rears its head once KVM uses u64 instead of uint64_t. No functional change intended. Signed-off-by: David Matlack <dmatlack@google.com> [sean: rename pread_uint64() => pread_u64, expand on types.h include] Link: https://patch.msgid.link/20260420212004.3938325-5-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
125 lines
4.1 KiB
C
125 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2023, Tencent, Inc.
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*/
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#ifndef SELFTEST_KVM_PMU_H
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#define SELFTEST_KVM_PMU_H
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#include <stdbool.h>
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#include <linux/types.h>
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#include <linux/bits.h>
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#define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300
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/*
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* Encode an eventsel+umask pair into event-select MSR format. Note, this is
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* technically AMD's format, as Intel's format only supports 8 bits for the
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* event selector, i.e. doesn't use bits 24:16 for the selector. But, OR-ing
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* in '0' is a nop and won't clobber the CMASK.
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*/
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#define RAW_EVENT(eventsel, umask) (((eventsel & 0xf00UL) << 24) | \
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((eventsel) & 0xff) | \
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((umask) & 0xff) << 8)
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/*
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* These are technically Intel's definitions, but except for CMASK (see above),
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* AMD's layout is compatible with Intel's.
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*/
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#define ARCH_PERFMON_EVENTSEL_EVENT GENMASK_ULL(7, 0)
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#define ARCH_PERFMON_EVENTSEL_UMASK GENMASK_ULL(15, 8)
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#define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16)
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#define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17)
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#define ARCH_PERFMON_EVENTSEL_EDGE BIT_ULL(18)
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#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL BIT_ULL(19)
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#define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20)
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#define ARCH_PERFMON_EVENTSEL_ANY BIT_ULL(21)
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#define ARCH_PERFMON_EVENTSEL_ENABLE BIT_ULL(22)
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#define ARCH_PERFMON_EVENTSEL_INV BIT_ULL(23)
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#define ARCH_PERFMON_EVENTSEL_CMASK GENMASK_ULL(31, 24)
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/* RDPMC control flags, Intel only. */
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#define INTEL_RDPMC_METRICS BIT_ULL(29)
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#define INTEL_RDPMC_FIXED BIT_ULL(30)
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#define INTEL_RDPMC_FAST BIT_ULL(31)
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/* Fixed PMC controls, Intel only. */
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#define FIXED_PMC_GLOBAL_CTRL_ENABLE(_idx) BIT_ULL((32 + (_idx)))
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#define FIXED_PMC_KERNEL BIT_ULL(0)
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#define FIXED_PMC_USER BIT_ULL(1)
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#define FIXED_PMC_ANYTHREAD BIT_ULL(2)
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#define FIXED_PMC_ENABLE_PMI BIT_ULL(3)
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#define FIXED_PMC_NR_BITS 4
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#define FIXED_PMC_CTRL(_idx, _val) ((_val) << ((_idx) * FIXED_PMC_NR_BITS))
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#define PMU_CAP_FW_WRITES BIT_ULL(13)
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#define PMU_CAP_LBR_FMT 0x3f
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#define INTEL_ARCH_CPU_CYCLES RAW_EVENT(0x3c, 0x00)
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#define INTEL_ARCH_INSTRUCTIONS_RETIRED RAW_EVENT(0xc0, 0x00)
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#define INTEL_ARCH_REFERENCE_CYCLES RAW_EVENT(0x3c, 0x01)
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#define INTEL_ARCH_LLC_REFERENCES RAW_EVENT(0x2e, 0x4f)
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#define INTEL_ARCH_LLC_MISSES RAW_EVENT(0x2e, 0x41)
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#define INTEL_ARCH_BRANCHES_RETIRED RAW_EVENT(0xc4, 0x00)
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#define INTEL_ARCH_BRANCHES_MISPREDICTED RAW_EVENT(0xc5, 0x00)
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#define INTEL_ARCH_TOPDOWN_SLOTS RAW_EVENT(0xa4, 0x01)
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#define INTEL_ARCH_TOPDOWN_BE_BOUND RAW_EVENT(0xa4, 0x02)
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#define INTEL_ARCH_TOPDOWN_BAD_SPEC RAW_EVENT(0x73, 0x00)
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#define INTEL_ARCH_TOPDOWN_FE_BOUND RAW_EVENT(0x9c, 0x01)
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#define INTEL_ARCH_TOPDOWN_RETIRING RAW_EVENT(0xc2, 0x02)
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#define INTEL_ARCH_LBR_INSERTS RAW_EVENT(0xe4, 0x01)
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#define AMD_ZEN_CORE_CYCLES RAW_EVENT(0x76, 0x00)
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#define AMD_ZEN_INSTRUCTIONS_RETIRED RAW_EVENT(0xc0, 0x00)
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#define AMD_ZEN_BRANCHES_RETIRED RAW_EVENT(0xc2, 0x00)
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#define AMD_ZEN_BRANCHES_MISPREDICTED RAW_EVENT(0xc3, 0x00)
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/*
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* Note! The order and thus the index of the architectural events matters as
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* support for each event is enumerated via CPUID using the index of the event.
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*/
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enum intel_pmu_architectural_events {
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INTEL_ARCH_CPU_CYCLES_INDEX,
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INTEL_ARCH_INSTRUCTIONS_RETIRED_INDEX,
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INTEL_ARCH_REFERENCE_CYCLES_INDEX,
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INTEL_ARCH_LLC_REFERENCES_INDEX,
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INTEL_ARCH_LLC_MISSES_INDEX,
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INTEL_ARCH_BRANCHES_RETIRED_INDEX,
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INTEL_ARCH_BRANCHES_MISPREDICTED_INDEX,
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INTEL_ARCH_TOPDOWN_SLOTS_INDEX,
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INTEL_ARCH_TOPDOWN_BE_BOUND_INDEX,
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INTEL_ARCH_TOPDOWN_BAD_SPEC_INDEX,
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INTEL_ARCH_TOPDOWN_FE_BOUND_INDEX,
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INTEL_ARCH_TOPDOWN_RETIRING_INDEX,
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INTEL_ARCH_LBR_INSERTS_INDEX,
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NR_INTEL_ARCH_EVENTS,
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};
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enum amd_pmu_zen_events {
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AMD_ZEN_CORE_CYCLES_INDEX,
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AMD_ZEN_INSTRUCTIONS_INDEX,
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AMD_ZEN_BRANCHES_INDEX,
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AMD_ZEN_BRANCH_MISSES_INDEX,
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NR_AMD_ZEN_EVENTS,
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};
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extern const u64 intel_pmu_arch_events[];
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extern const u64 amd_pmu_zen_events[];
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enum pmu_errata {
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INSTRUCTIONS_RETIRED_OVERCOUNT,
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BRANCHES_RETIRED_OVERCOUNT,
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};
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extern u64 pmu_errata_mask;
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void kvm_init_pmu_errata(void);
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static inline bool this_pmu_has_errata(enum pmu_errata errata)
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{
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return pmu_errata_mask & BIT_ULL(errata);
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}
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#endif /* SELFTEST_KVM_PMU_H */
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