Maher Sanalla 967bd1254f net/mlx5: Expose shared buffer registers bits and structs ...

[ Upstream commit 8d231dbc3b ]

Add the shared receive buffer management and configuration registers:
1. SBPR - Shared Buffer Pools Register
2. SBCM - Shared Buffer Class Management Register

Signed-off-by: Maher Sanalla <msanalla@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Stable-dep-of: 9fcc2b6c10 ("net/mlx5e: Fix potentially misleading debug message")
Signed-off-by: Sasha Levin <sashal@kernel.org>

2025-12-07 06:12:33 +09:00

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cq.h

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device.h

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doorbell.h

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driver.h

net/mlx5: Expose shared buffer registers bits and structs

2025-12-07 06:12:33 +09:00

eq.h

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eswitch.h

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fs_helpers.h

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fs.h

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mlx5_ifc_fpga.h

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mlx5_ifc_vdpa.h

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mlx5_ifc.h

net/mlx5: Expose shared buffer registers bits and structs

2025-12-07 06:12:33 +09:00

mpfs.h

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port.h

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qp.h

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rsc_dump.h

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transobj.h

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vport.h

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