Hiroshi DOYU 774dfc9bb7 iommu/tegra: gart: Fix register offset correctly ...

DT passes the exact GART register ranges without any overlapping with
MC register ranges. GART register offset needs to be adjusted by one
passed by DT correctly.

Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

2012-05-11 11:42:05 +02:00

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nvidia,tegra20-gart.txt

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