Cristian Ciocaltea d2b58a1022 drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI0 ...

[ Upstream commit 2c1268e7aa ]

The RK3588 specific implementation is currently quite limited in terms
of handling the full range of display modes supported by the connected
screens, e.g. 2560x1440@75Hz, 2048x1152@60Hz, 1024x768@60Hz are just a
few of them.

Additionally, it doesn't cope well with non-integer refresh rates like
59.94, 29.97, 23.98, etc.

Make use of HDMI0 PHY PLL as a more accurate DCLK source to handle
all display modes up to 4K@60Hz.

Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20250204-vop2-hdmi0-disp-modes-v3-3-d71c6a196e58@collabora.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

2025-05-29 11:03:00 +02:00

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analogix_dp-rockchip.c

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cdn-dp-core.c

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cdn-dp-core.h

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cdn-dp-reg.c

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cdn-dp-reg.h

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dw_hdmi-rockchip.c

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dw-mipi-dsi-rockchip.c

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inno_hdmi.c

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inno_hdmi.h

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Kconfig

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Makefile

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rk3066_hdmi.c

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rk3066_hdmi.h

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rockchip_drm_drv.c

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rockchip_drm_drv.h

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rockchip_drm_fb.c

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rockchip_drm_fb.h

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rockchip_drm_gem.c

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rockchip_drm_gem.h

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rockchip_drm_vop2.c

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rockchip_drm_vop2.h

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rockchip_drm_vop.c

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rockchip_drm_vop.h

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rockchip_lvds.c

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rockchip_lvds.h

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rockchip_rgb.c

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rockchip_rgb.h

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rockchip_vop2_reg.c

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rockchip_vop_reg.c

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rockchip_vop_reg.h

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