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linux-stable-mirror/arch/riscv/kernel
Andreas Schwab 95a13b0a6b riscv: traps_misaligned: properly sign extend value in misaligned load handler
[ Upstream commit b3510183ab ]

Add missing cast to signed long.

Signed-off-by: Andreas Schwab <schwab@suse.de>
Fixes: 956d705dd2 ("riscv: Unaligned load/store handling for M_MODE")
Tested-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/mvmikk0goil.fsf@suse.de
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2025-07-24 08:56:32 +02:00
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