Files
linux-stable-mirror/arch/mips/include/asm
Jiaxun Yang 4a3e37b3ca MIPS: mipsmtregs: Fix target register for MFTC0
Target register of mftc0 should be __res instead of $1, this is
a leftover from old .insn code.

Fixes: dd6d29a614 ("MIPS: Implement microMIPS MT ASE helpers")
Cc: stable@vger.kernel.org
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2024-06-21 10:16:15 +02:00
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