Shawn LinandSasha Levin ddfe47664c PCI: dw-rockchip: Disable BAR 0 and BAR 1 for Root Port ...

[ Upstream commit b5d712e5b8 ]

Some Rockchip PCIe Root Ports report bogus size of 1GiB for the BAR
memories and they cause below resource allocation issue during probe.

  pci 0000:00:00.0: [1d87:3588] type 01 class 0x060400 PCIe Root Port
  pci 0000:00:00.0: BAR 0 [mem 0x00000000-0x3fffffff]
  pci 0000:00:00.0: BAR 1 [mem 0x00000000-0x3fffffff]
  pci 0000:00:00.0: ROM [mem 0x00000000-0x0000ffff pref]
	...
  pci 0000:00:00.0: BAR 0 [mem 0x900000000-0x93fffffff]: assigned
  pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: can't assign; no space
  pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: failed to assign
  pci 0000:00:00.0: ROM [mem 0xf0200000-0xf020ffff pref]: assigned
  pci 0000:00:00.0: BAR 0 [mem 0x900000000-0x93fffffff]: releasing
  pci 0000:00:00.0: ROM [mem 0xf0200000-0xf020ffff pref]: releasing
  pci 0000:00:00.0: BAR 0 [mem 0x900000000-0x93fffffff]: assigned
  pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: can't assign; no space
  pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: failed to assign

Since there is no use of the Root Port BAR memories, disable both of them.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
[mani: reworded the description and comment]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/1766570461-138256-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

2026-03-04 07:20:45 -05:00

..

cadence

PCI: cadence: Check for the existence of cdns_pcie::ops before using it

2025-11-24 10:29:42 +01:00

dwc

PCI: dw-rockchip: Disable BAR 0 and BAR 1 for Root Port

2026-03-04 07:20:45 -05:00

mobiveil

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Kconfig

PCI: rcar-gen2: Drop ARM dependency from PCI_RCAR_GEN2

2026-01-11 15:21:15 +01:00

Makefile

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pci-aardvark.c

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pci-ftpci100.c

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pci-host-common.c

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pci-host-generic.c

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pci-hyperv-intf.c

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pci-hyperv.c

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pci-ixp4xx.c

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pci-loongson.c

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pci-mvebu.c

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pci-rcar-gen2.c

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pci-tegra.c

PCI: tegra: Convert struct tegra_msi mask_lock into raw spinlock

2025-10-19 16:30:53 +02:00

pci-thunder-ecam.c

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pci-thunder-pem.c

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pci-v3-semi.c

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pci-versatile.c

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pci-xgene-msi.c

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pci-xgene.c

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pcie-altera-msi.c

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pcie-altera.c

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pcie-apple.c

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pcie-brcmstb.c

PCI: brcmstb: Fix disabling L0s capability

2026-01-11 15:22:23 +01:00

pcie-hisi-error.c

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pcie-iproc-bcma.c

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pcie-iproc-msi.c

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pcie-iproc-platform.c

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pcie-iproc.c

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pcie-iproc.h

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pcie-mediatek-gen3.c

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pcie-mediatek.c

PCI: mediatek: Fix IRQ domain leak when MSI allocation fails

2026-03-04 07:19:42 -05:00

pcie-microchip-host.c

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pcie-mt7621.c

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pcie-rcar-ep.c

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pcie-rcar-host.c

PCI: rcar-host: Convert struct rcar_msi mask_lock into raw spinlock

2025-10-19 16:30:54 +02:00

pcie-rcar.c

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pcie-rcar.h

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pcie-rockchip-ep.c

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pcie-rockchip-host.c

PCI: rockchip: Set Target Link Speed to 5.0 GT/s before retraining

2025-08-28 16:28:44 +02:00

pcie-rockchip.c

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pcie-rockchip.h

PCI: rockchip: Use standard PCIe definitions

2025-08-28 16:28:44 +02:00

pcie-xilinx-cpm.c

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pcie-xilinx-nwl.c

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pcie-xilinx.c

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vmd.c

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