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Deepak Gupta
9d42fc28fc
The Zicfiss and Zicfilp extensions introduce a new exception, the 'software check exception', in the privileged ISA, with cause code = 18. This patch implements support for software check exceptions. Additionally, the patch implements a CFI violation handler which checks the code in the xtval register. If xtval=2, the software check exception happened because of an indirect branch that didn't land on a 4 byte aligned PC or on a 'lpad' instruction, or the label value embedded in 'lpad' didn't match the label value set in the x7 register. If xtval=3, the software check exception happened due to a mismatch between the link register (x1 or x5) and the top of shadow stack (on execution of `sspopchk`). In case of a CFI violation, SIGSEGV is raised with code=SEGV_CPERR. SEGV_CPERR was introduced by the x86 shadow stack patches. To keep uprobes working, handle the uprobe event first before reporting the CFI violation in the software check exception handler. This is because, when the landing pad is activated, if the uprobe point is set at the lpad instruction at the beginning of a function, the system triggers a software check exception instead of an ebreak exception due to the exception priority. This would prevent uprobe from working. Reviewed-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-15-b55691eacf4f@rivosinc.com [pjw@kernel.org: cleaned up the patch description] Signed-off-by: Paul Walmsley <pjw@kernel.org>
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_RISCV_ENTRY_COMMON_H
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#define _ASM_RISCV_ENTRY_COMMON_H
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#include <asm/stacktrace.h>
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#include <asm/thread_info.h>
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#include <asm/vector.h>
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static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs,
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unsigned long ti_work)
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{
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if (ti_work & _TIF_RISCV_V_DEFER_RESTORE) {
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clear_thread_flag(TIF_RISCV_V_DEFER_RESTORE);
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/*
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* We are already called with irq disabled, so go without
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* keeping track of riscv_v_flags.
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*/
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riscv_v_vstate_restore(¤t->thread.vstate, regs);
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}
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}
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#define arch_exit_to_user_mode_prepare arch_exit_to_user_mode_prepare
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void handle_page_fault(struct pt_regs *regs);
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void handle_break(struct pt_regs *regs);
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#ifdef CONFIG_RISCV_MISALIGNED
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int handle_misaligned_load(struct pt_regs *regs);
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int handle_misaligned_store(struct pt_regs *regs);
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#else
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static inline int handle_misaligned_load(struct pt_regs *regs)
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{
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return -1;
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}
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static inline int handle_misaligned_store(struct pt_regs *regs)
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{
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return -1;
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}
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#endif
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bool handle_user_cfi_violation(struct pt_regs *regs);
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#endif /* _ASM_RISCV_ENTRY_COMMON_H */
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